DMA Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	1.269ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	1.905ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	337.511us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	204.636us	1	1	100.00
V1	csr_rw	dma_csr_rw	5.000s	55.540us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	12.000s	512.132us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	81.046us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	59.724us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	55.540us	1	1	100.00
		dma_csr_aliasing	6.000s	81.046us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.533m	26.266ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	32.967m	729.440ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	6.767m	139.117ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	5.433m	99.537ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	32.967m	729.440ms	1	1	100.00
V2	dma_abort	dma_abort	10.000s	2.245ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.717m	8.539ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	14.670us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	24.565us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	24.565us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	204.636us	1	1	100.00
		dma_csr_rw	5.000s	55.540us	1	1	100.00
		dma_csr_aliasing	6.000s	81.046us	1	1	100.00
		dma_same_csr_outstanding	4.000s	150.550us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	204.636us	1	1	100.00
		dma_csr_rw	5.000s	55.540us	1	1	100.00
		dma_csr_aliasing	6.000s	81.046us	1	1	100.00
		dma_same_csr_outstanding	4.000s	150.550us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	27.000s	1.148ms	1	1	100.00
		dma_generic_stress	5.433m	99.537ms	1	1	100.00
		dma_handshake_stress	32.967m	729.440ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	277.326us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.650m	37.253ms	1	1	100.00
		dma_longer_transfer	5.000s	169.825us	1	1	100.00
		TOTAL			21	21	100.00