| V1 |
smoke |
hmac_smoke |
9.980s |
1.025ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
hmac_csr_hw_reset |
1.840s |
70.492us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
hmac_csr_rw |
1.520s |
20.881us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
hmac_csr_bit_bash |
7.900s |
2.703ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
hmac_csr_aliasing |
3.320s |
450.187us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
hmac_csr_mem_rw_with_rand_reset |
2.580s |
212.262us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
hmac_csr_rw |
1.520s |
20.881us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
3.320s |
450.187us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
long_msg |
hmac_long_msg |
39.770s |
3.083ms |
1 |
1 |
100.00 |
| V2 |
back_pressure |
hmac_back_pressure |
37.120s |
3.151ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
hmac_test_sha256_vectors |
8.520s |
187.833us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
19.600s |
2.251ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.351m |
52.345ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
6.450s |
191.607us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
9.270s |
1.730ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
9.230s |
539.724us |
1 |
1 |
100.00 |
| V2 |
burst_wr |
hmac_burst_wr |
8.650s |
2.317ms |
1 |
1 |
100.00 |
| V2 |
datapath_stress |
hmac_datapath_stress |
4.067m |
12.486ms |
1 |
1 |
100.00 |
| V2 |
error |
hmac_error |
58.740s |
21.242ms |
1 |
1 |
100.00 |
| V2 |
wipe_secret |
hmac_wipe_secret |
1.258m |
12.726ms |
1 |
1 |
100.00 |
| V2 |
save_and_restore |
hmac_smoke |
9.980s |
1.025ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
39.770s |
3.083ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
37.120s |
3.151ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
4.067m |
12.486ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
8.650s |
2.317ms |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
1.450s |
31.925us |
1 |
1 |
100.00 |
| V2 |
fifo_empty_status_interrupt |
hmac_smoke |
9.980s |
1.025ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
39.770s |
3.083ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
37.120s |
3.151ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
4.067m |
12.486ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.258m |
12.726ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
8.520s |
187.833us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
19.600s |
2.251ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.351m |
52.345ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
6.450s |
191.607us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
9.270s |
1.730ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
9.230s |
539.724us |
1 |
1 |
100.00 |
| V2 |
wide_digest_configurable_key_length |
hmac_smoke |
9.980s |
1.025ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
39.770s |
3.083ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
37.120s |
3.151ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
4.067m |
12.486ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
8.650s |
2.317ms |
1 |
1 |
100.00 |
|
|
hmac_error |
58.740s |
21.242ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.258m |
12.726ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
8.520s |
187.833us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
19.600s |
2.251ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.351m |
52.345ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
6.450s |
191.607us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
9.270s |
1.730ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
9.230s |
539.724us |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
1.450s |
31.925us |
1 |
1 |
100.00 |
| V2 |
stress_all |
hmac_stress_all |
1.450s |
31.925us |
1 |
1 |
100.00 |
| V2 |
alert_test |
hmac_alert_test |
1.520s |
34.878us |
1 |
1 |
100.00 |
| V2 |
intr_test |
hmac_intr_test |
1.440s |
16.370us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
hmac_tl_errors |
3.370s |
131.635us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
hmac_tl_errors |
3.370s |
131.635us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
hmac_csr_hw_reset |
1.840s |
70.492us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.520s |
20.881us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
3.320s |
450.187us |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
2.290s |
90.850us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
hmac_csr_hw_reset |
1.840s |
70.492us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.520s |
20.881us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
3.320s |
450.187us |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
2.290s |
90.850us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
17 |
17 |
100.00 |
| V2S |
tl_intg_err |
hmac_sec_cm |
1.860s |
307.616us |
1 |
1 |
100.00 |
|
|
hmac_tl_intg_err |
2.310s |
53.998us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
hmac_tl_intg_err |
2.310s |
53.998us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
write_config_and_secret_key_during_msg_wr |
hmac_smoke |
9.980s |
1.025ms |
1 |
1 |
100.00 |
| V3 |
stress_reset |
hmac_stress_reset |
1.850s |
128.440us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
hmac_stress_all_with_rand_reset |
17.300s |
1.870ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
hmac_directed |
4.820s |
424.724us |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
28 |
28 |
100.00 |