I2C Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: `6f17fda`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	13.390s	1.434ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	22.870s	1.050ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.480s	35.721us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.590s	32.432us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.160s	1.451ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.510s	95.156us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.800s	37.022us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.590s	32.432us	1	1	100.00
		i2c_csr_aliasing	2.510s	95.156us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.400s	139.875us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	17.268m	66.050ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.214m	5.406ms	1	1	100.00
V2	host_override	i2c_host_override	1.480s	27.819us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.752m	8.514ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	36.870s	6.871ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.900s	156.617us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.840s	345.372us	1	1	100.00
		i2c_host_fifo_reset_rx	3.980s	705.171us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	28.510s	7.307ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.010s	821.443us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.480s	124.161us	1	1	100.00
V2	target_glitch	i2c_target_glitch	6.620s	7.234ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	8.022m	75.041ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.080s	14.143ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	8.000s	1.115ms	1	1	100.00
		i2c_target_intr_smoke	4.400s	4.364ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.910s	155.096us	1	1	100.00
		i2c_target_fifo_reset_tx	1.820s	236.378us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	7.770s	8.447ms	1	1	100.00
		i2c_target_stress_rd	8.000s	1.115ms	1	1	100.00
		i2c_target_intr_stress_wr	52.630s	25.398ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.530s	1.464ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.930s	832.153us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.390s	4.273ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	6.140s	10.025ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.150s	450.236us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.640s	147.401us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.214m	5.406ms	1	1	100.00
		i2c_host_perf_precise	3.400s	61.448us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.010s	821.443us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.290s	90.006us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.750s	602.275us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.920s	3.974ms	1	1	100.00
		i2c_target_nack_txstretch	1.960s	140.532us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	6.210s	635.300us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.650s	879.496us	1	1	100.00
V2	alert_test	i2c_alert_test	1.800s	19.140us	1	1	100.00
V2	intr_test	i2c_intr_test	1.710s	25.234us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.930s	463.018us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.930s	463.018us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.480s	35.721us	1	1	100.00
		i2c_csr_rw	1.590s	32.432us	1	1	100.00
		i2c_csr_aliasing	2.510s	95.156us	1	1	100.00
		i2c_same_csr_outstanding	1.810s	62.591us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.480s	35.721us	1	1	100.00
		i2c_csr_rw	1.590s	32.432us	1	1	100.00
		i2c_csr_aliasing	2.510s	95.156us	1	1	100.00
		i2c_same_csr_outstanding	1.810s	62.591us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.050s	588.307us	1	1	100.00
		i2c_sec_cm	1.670s	41.651us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.050s	588.307us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.130s	1.395ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.750s	103.209us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	2.430s	57.934us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 2 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.5790852648340946396776625571461420317636768195849529977298278610613917152634
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 103209008 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 155 [0x9b])
  UVM_INFO @ 103209008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.78742596556621104497979838640366836936715813065735051483119294306242178141825
    Line 99, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  57934237 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 100 [0x64])
  UVM_INFO @  57934237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.43827081843615678456979599599284012076635416351070697530134977000847922849860
Line 237, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 66049791169 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @23554172

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.101457044059422296290165779245692647899041303506797225138510918806013017399692
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10024840920 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10024840920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.92305136778922711507823080030763952589912745535405782821235091494310315415366
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1394713170 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1394713170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```