KEYMGR Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.900s	129.137us	1	1	100.00
V1	random	keymgr_random	6.870s	2.558ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.100s	60.524us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.770s	33.202us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.160s	136.024us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.970s	1.423ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.060s	35.905us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.770s	33.202us	1	1	100.00
		keymgr_csr_aliasing	9.970s	1.423ms	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	2.730s	114.968us	1	1	100.00
V2	sideload	keymgr_sideload	3.760s	219.287us	1	1	100.00
		keymgr_sideload_kmac	17.650s	827.392us	1	1	100.00
		keymgr_sideload_aes	3.050s	60.721us	1	1	100.00
		keymgr_sideload_otbn	2.760s	63.505us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	8.470s	2.876ms	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.070s	153.170us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.480s	124.960us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.540s	55.944us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.620s	238.499us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.530s	156.463us	1	1	100.00
V2	stress_all	keymgr_stress_all	41.620s	6.188ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.600s	9.712us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.710s	34.726us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.510s	31.538us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.510s	31.538us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.100s	60.524us	1	1	100.00
		keymgr_csr_rw	1.770s	33.202us	1	1	100.00
		keymgr_csr_aliasing	9.970s	1.423ms	1	1	100.00
		keymgr_same_csr_outstanding	2.340s	44.494us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.100s	60.524us	1	1	100.00
		keymgr_csr_rw	1.770s	33.202us	1	1	100.00
		keymgr_csr_aliasing	9.970s	1.423ms	1	1	100.00
		keymgr_same_csr_outstanding	2.340s	44.494us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
		keymgr_tl_intg_err	2.410s	161.807us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.860s	195.954us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.860s	195.954us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.860s	195.954us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.860s	195.954us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	11.620s	838.013us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.410s	161.807us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.860s	195.954us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.730s	114.968us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	6.870s	2.558ms	1	1	100.00
		keymgr_csr_rw	1.770s	33.202us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	6.870s	2.558ms	1	1	100.00
		keymgr_csr_rw	1.770s	33.202us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	6.870s	2.558ms	1	1	100.00
		keymgr_csr_rw	1.770s	33.202us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.070s	153.170us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.620s	238.499us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.620s	238.499us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	6.870s	2.558ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.030s	254.861us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	6.170s	528.411us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.070s	153.170us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	6.170s	528.411us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	6.170s	528.411us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	6.170s	528.411us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.900s	2.313ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	6.170s	528.411us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	8.630s	445.568us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.68251313954420617400470086586293867175400534764214456055640537444423603400312
      Line 122, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
        UVM_ERROR @ 161807216 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
        UVM_INFO @ 161807216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.100145432755843694654514288931285426864291661677876378922715423450967250992986
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
        UVM_ERROR @  35904551 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
        UVM_INFO @  35904551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:333) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.15703474832876324786455780486157476740822877142972057020671536271957000039001
      Line 1384, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 445567853 ps: (cip_base_scoreboard.sv:333) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 445567853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---