KMAC/MASKED Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	34.160s	19.971ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.790s	71.964us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.070s	21.473us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.870s	760.288us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.880s	767.837us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.600s	561.856us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.070s	21.473us	1	1	100.00
		kmac_csr_aliasing	6.880s	767.837us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.670s	10.509us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.880s	34.278us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.292m	2.771ms	1	1	100.00
V2	burst_write	kmac_burst_write	19.080m	14.098ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.210s	4.793ms	1	1	100.00
		kmac_test_vectors_sha3_256	33.640s	3.505ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.950s	5.809ms	1	1	100.00
		kmac_test_vectors_sha3_512	19.582m	506.749ms	1	1	100.00
		kmac_test_vectors_shake_128	37.364m	113.461ms	1	1	100.00
		kmac_test_vectors_shake_256	29.791m	649.854ms	1	1	100.00
		kmac_test_vectors_kmac	2.880s	782.503us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.890s	413.551us	1	1	100.00
V2	sideload	kmac_sideload	4.813m	19.694ms	1	1	100.00
V2	app	kmac_app	33.020s	878.553us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.829m	7.752ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	51.730s	3.405ms	1	1	100.00
V2	error	kmac_error	2.400m	10.285ms	1	1	100.00
V2	key_error	kmac_key_error	4.900s	899.118us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.170s	496.248us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	10.000s	1.221ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.870s	25.777us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	25.720s	1.931ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.110s	47.439us	1	1	100.00
V2	stress_all	kmac_stress_all	52.790s	9.670ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.500s	13.813us	1	1	100.00
V2	alert_test	kmac_alert_test	2.030s	70.023us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.070s	41.977us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.070s	41.977us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.790s	71.964us	1	1	100.00
		kmac_csr_rw	2.070s	21.473us	1	1	100.00
		kmac_csr_aliasing	6.880s	767.837us	1	1	100.00
		kmac_same_csr_outstanding	1.990s	21.841us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.790s	71.964us	1	1	100.00
		kmac_csr_rw	2.070s	21.473us	1	1	100.00
		kmac_csr_aliasing	6.880s	767.837us	1	1	100.00
		kmac_same_csr_outstanding	1.990s	21.841us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.360s	67.977us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.360s	67.977us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.360s	67.977us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.360s	67.977us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.820s	93.824us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	38.080s	4.212ms	1	1	100.00
		kmac_tl_intg_err	1.730s	60.370us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.730s	60.370us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.110s	47.439us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	34.160s	19.971ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.813m	19.694ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.360s	67.977us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	38.080s	4.212ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	38.080s	4.212ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	38.080s	4.212ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	34.160s	19.971ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.110s	47.439us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	38.080s	4.212ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.280m	10.746ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	34.160s	19.971ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.938m	4.928ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.8997523103942613341240693228268479818340257955557877887602333673925649804342
      Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
        UVM_ERROR @  60369917 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
        UVM_INFO @  60369917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---