KMAC/UNMASKED Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	14.100s	4.018ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.800s	56.957us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.920s	57.044us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.570s	2.763ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.210s	1.245ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.240s	78.921us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.920s	57.044us	1	1	100.00
		kmac_csr_aliasing	8.210s	1.245ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.780s	24.509us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.880s	55.013us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	36.407m	114.836ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.269m	67.778ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.089m	240.602ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.697m	118.321ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.320s	1.542ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.240s	2.801ms	1	1	100.00
		kmac_test_vectors_shake_128	2.419m	82.742ms	1	1	100.00
		kmac_test_vectors_shake_256	1.407m	18.845ms	1	1	100.00
		kmac_test_vectors_kmac	2.860s	89.169us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.070s	1.349ms	1	1	100.00
V2	sideload	kmac_sideload	1.519m	5.824ms	1	1	100.00
V2	app	kmac_app	36.930s	3.159ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	30.310s	1.541ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	10.430s	273.507us	1	1	100.00
V2	error	kmac_error	2.232m	2.801ms	1	1	100.00
V2	key_error	kmac_key_error	9.860s	6.301ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.120s	35.425us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.850s	287.029us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	14.120s	4.266ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	20.830s	2.598ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.050s	55.176us	1	1	100.00
V2	stress_all	kmac_stress_all	9.580m	49.346ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.730s	62.412us	1	1	100.00
V2	alert_test	kmac_alert_test	1.630s	21.262us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.680s	1.061ms	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.680s	1.061ms	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.800s	56.957us	1	1	100.00
		kmac_csr_rw	1.920s	57.044us	1	1	100.00
		kmac_csr_aliasing	8.210s	1.245ms	1	1	100.00
		kmac_same_csr_outstanding	2.900s	146.354us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.800s	56.957us	1	1	100.00
		kmac_csr_rw	1.920s	57.044us	1	1	100.00
		kmac_csr_aliasing	8.210s	1.245ms	1	1	100.00
		kmac_same_csr_outstanding	2.900s	146.354us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.710s	105.832us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.710s	105.832us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.710s	105.832us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.710s	105.832us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.870s	341.272us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	22.800s	3.770ms	1	1	100.00
		kmac_tl_intg_err	1.800s	13.637us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.800s	13.637us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.050s	55.176us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	14.100s	4.018ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.519m	5.824ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.710s	105.832us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	22.800s	3.770ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	22.800s	3.770ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	22.800s	3.770ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	14.100s	4.018ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.050s	55.176us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	22.800s	3.770ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.371m	8.438ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	14.100s	4.018ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.024m	7.391ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.48876252979046753504301247601908832217385772149856810009813248587952264767756
      Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
        UVM_ERROR @  13636757 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
        UVM_INFO @  13636757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---