6f17fda| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 59.000s | 12.766ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 26.779us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 3.000s | 14.021us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 82.757us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 35.662us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 3.000s | 865.118ns | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 3.000s | 14.021us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 35.662us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 34.000s | 9.207ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 35.000s | 749.880us | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 35.000s | 858.392us | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 17.001us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 1.999us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 1.999us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 26.779us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 14.021us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 35.662us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 20.221us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 26.779us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 14.021us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 35.662us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 20.221us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 36.809us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 11.986us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_errors has 1 failures.
0.mbx_tl_errors.110992779503809653443732778936019727699508727369033918254977466601695197336216
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1999067 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x508f6cc3 a_data = 0x39b4de76 a_mask = 0x3 a_size = 0x0 a_param = 0x0 a_source = 0xe7 a_opcode = PutPartialData a_user = 0x2468a d_data = 0x66c63d1b d_size = 0x1 d_param = 0x0 d_source = 0x8d d_opcode = AccessAck d_error = 0 d_user = 10110101001101 d_sink = 0 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1999067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_csr_mem_rw_with_rand_reset has 1 failures.
0.mbx_csr_mem_rw_with_rand_reset.94364077150391738521945322430471433731221042203592300495863185308604078797482
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 865118 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xbd7b519 a_data = 0xa32162bc a_mask = 0xc a_size = 0x0 a_param = 0x0 a_source = 0xa a_opcode = PutPartialData a_user = 0x27d0b d_data = 0x5a9cead7 d_size = 0x1 d_param = 0x0 d_source = 0xf1 d_opcode = AccessAck d_error = 0 d_user = 1101101110000 d_sink = 1 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 865118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.70300320151970540795645637046612745172686647752803553917597952332473597587352
Line 99, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 11986120 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xbee6a82c a_data = 0x8484cbd3 a_mask = 0x2 a_size = 0x1 a_param = 0x0 a_source = 0x9f a_opcode = Get a_user = 0x251e2 d_data = 0x52fae07a d_size = 0x0 d_param = 0x0 d_source = 0x93 d_opcode = AccessAckData d_error = 0 d_user = 101100101010 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 11986120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---