OTBN Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	39.466us	1	1	100.00
V1	single_binary	otbn_single	9.000s	12.097us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	25.348us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	45.412us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	105.007us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	19.344us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	227.763us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	45.412us	1	1	100.00
		otbn_csr_aliasing	7.000s	19.344us	1	1	100.00
V1	mem_walk	otbn_mem_walk	20.000s	735.265us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	13.000s	756.790us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	23.000s	150.788us	1	1	100.00
V2	multi_error	otbn_multi_err	42.000s	497.651us	1	1	100.00
V2	back_to_back	otbn_multi	1.650m	836.161us	1	1	100.00
V2	stress_all	otbn_stress_all	1.083m	466.747us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	22.566us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	128.582us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	9.000s	17.928us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	141.540us	1	1	100.00
V2	intr_test	otbn_intr_test	7.000s	12.423us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	38.184us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	38.184us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	25.348us	1	1	100.00
		otbn_csr_rw	6.000s	45.412us	1	1	100.00
		otbn_csr_aliasing	7.000s	19.344us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	20.595us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	25.348us	1	1	100.00
		otbn_csr_rw	6.000s	45.412us	1	1	100.00
		otbn_csr_aliasing	7.000s	19.344us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	20.595us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	116.724us	1	1	100.00
		otbn_dmem_err	10.000s	67.540us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	219.242us	1	1	100.00
		otbn_controller_ispr_rdata_err	8.000s	16.426us	1	1	100.00
		otbn_mac_bignum_acc_err	11.000s	59.423us	1	1	100.00
		otbn_urnd_err	8.000s	24.236us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	25.052us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	15.558us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	25.085us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	2.567m	3.590ms	1	1	100.00
		otbn_tl_intg_err	18.000s	471.030us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	14.000s	1.328ms	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	39.466us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	10.000s	67.540us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	116.724us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	18.000s	471.030us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	22.566us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	116.724us	1	1	100.00
		otbn_dmem_err	10.000s	67.540us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	128.582us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	25.052us	1	1	100.00
		otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	12.097us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	116.724us	1	1	100.00
		otbn_dmem_err	10.000s	67.540us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	128.582us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	25.052us	1	1	100.00
		otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	22.566us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	116.724us	1	1	100.00
		otbn_dmem_err	10.000s	67.540us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	128.582us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	25.052us	1	1	100.00
		otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	12.097us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	18.367us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	19.353us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	57.000s	682.829us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	57.000s	682.829us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	16.247us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	164.946us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	27.631us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	27.631us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	60.719us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	12.097us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	12.097us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	12.097us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.650m	836.161us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	12.097us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	12.097us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	20.790us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	12.097us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	2.567m	3.590ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.817m	4.108ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			40	41	97.56

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.85727343241244084785549495796085414729913402115914056946767349590078287783702
      Line 114, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 60718930 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  60718930 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  60718930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---