ROM_CTRL/32KB Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.070s 562.606us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.150s 303.877us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.760s 339.873us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.230s 557.538us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.510s 1.035ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.020s 167.575us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.760s 339.873us 1 1 100.00
rom_ctrl_csr_aliasing 5.510s 1.035ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.130s 693.589us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.670s 165.917us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.260s 136.189us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 22.210s 8.358ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 9.340s 308.722us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.340s 558.439us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.310s 417.148us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.310s 417.148us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.150s 303.877us 1 1 100.00
rom_ctrl_csr_rw 4.760s 339.873us 1 1 100.00
rom_ctrl_csr_aliasing 5.510s 1.035ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.410s 132.799us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.150s 303.877us 1 1 100.00
rom_ctrl_csr_rw 4.760s 339.873us 1 1 100.00
rom_ctrl_csr_aliasing 5.510s 1.035ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.410s 132.799us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.646m 5.204ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 16.650s 3.858ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.064m 1.053ms 1 1 100.00
rom_ctrl_tl_intg_err 22.240s 498.532us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.064m 1.053ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.064m 1.053ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.646m 5.204ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.646m 5.204ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.646m 5.204ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.646m 5.204ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.646m 5.204ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.064m 1.053ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.064m 1.053ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.070s 562.606us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.070s 562.606us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.070s 562.606us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 22.240s 498.532us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.646m 5.204ms 1 1 100.00
rom_ctrl_kmac_err_chk 9.340s 308.722us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.646m 5.204ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.646m 5.204ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.646m 5.204ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 16.650s 3.858ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.064m 1.053ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 43.830s 1.636ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00