ROM_CTRL/64KB Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.980s 218.731us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.550s 801.719us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.430s 701.756us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.560s 294.371us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.720s 1.164ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.190s 218.523us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.430s 701.756us 1 1 100.00
rom_ctrl_csr_aliasing 6.720s 1.164ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.140s 1.489ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.690s 3.121ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.820s 313.789us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 28.550s 12.475ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.710s 386.186us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 8.710s 533.763us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.120s 207.629us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.120s 207.629us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.550s 801.719us 1 1 100.00
rom_ctrl_csr_rw 6.430s 701.756us 1 1 100.00
rom_ctrl_csr_aliasing 6.720s 1.164ms 1 1 100.00
rom_ctrl_same_csr_outstanding 9.330s 319.928us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.550s 801.719us 1 1 100.00
rom_ctrl_csr_rw 6.430s 701.756us 1 1 100.00
rom_ctrl_csr_aliasing 6.720s 1.164ms 1 1 100.00
rom_ctrl_same_csr_outstanding 9.330s 319.928us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.715m 2.787ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 33.330s 1.106ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.557m 1.004ms 1 1 100.00
rom_ctrl_tl_intg_err 1.085m 516.093us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.557m 1.004ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.557m 1.004ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.715m 2.787ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.715m 2.787ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.715m 2.787ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.715m 2.787ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.715m 2.787ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.557m 1.004ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.557m 1.004ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.980s 218.731us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.980s 218.731us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.980s 218.731us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.085m 516.093us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.715m 2.787ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.710s 386.186us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.715m 2.787ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.715m 2.787ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.715m 2.787ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 33.330s 1.106ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.557m 1.004ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.523m 9.438ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00