SPI_DEVICE/1R1W Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.179m	24.335ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.630s	16.468us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.270s	133.668us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	19.340s	3.482ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.860s	801.249us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.850s	372.807us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.270s	133.668us	1	1	100.00
		spi_device_csr_aliasing	11.860s	801.249us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.580s	45.794us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.630s	273.499us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.870s	19.211us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.540s	3.694us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.700s	1.607us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.490s	163.865us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.490s	163.865us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.170s	380.621us	1	1	100.00
		spi_device_tpm_sts_read	1.470s	61.658us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.010s	2.602ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.810s	899.888us	1	1	100.00
		spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	14.820s	25.516ms	1	1	100.00
		spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	14.820s	25.516ms	1	1	100.00
		spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.660s	116.446us	1	1	100.00
		spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.660s	116.446us	1	1	100.00
		spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.660s	116.446us	1	1	100.00
		spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.660s	116.446us	1	1	100.00
		spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.660s	116.446us	1	1	100.00
		spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.820s	113.416us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	13.950s	1.999ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	13.950s	1.999ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	13.950s	1.999ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.070s	1.038ms	1	1	100.00
		spi_device_read_buffer_direct	4.350s	165.632us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	13.950s	1.999ms	1	1	100.00
		spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.765m	66.882ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.100s	683.165us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.100s	683.165us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.179m	24.335ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.280m	518.134ms	1	1	100.00
V2	stress_all	spi_device_stress_all	46.410s	5.413ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.580s	19.141us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.550s	24.303us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.630s	1.367ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.630s	1.367ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.630s	16.468us	1	1	100.00
		spi_device_csr_rw	2.270s	133.668us	1	1	100.00
		spi_device_csr_aliasing	11.860s	801.249us	1	1	100.00
		spi_device_same_csr_outstanding	2.280s	47.469us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.630s	16.468us	1	1	100.00
		spi_device_csr_rw	2.270s	133.668us	1	1	100.00
		spi_device_csr_aliasing	11.860s	801.249us	1	1	100.00
		spi_device_same_csr_outstanding	2.280s	47.469us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.160s	39.657us	1	1	100.00
		spi_device_tl_intg_err	16.760s	3.933ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.760s	3.933ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	19.650s	1.432ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.6589213086026885812855026958886883144126122060531795433017552172984875084328
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2974447 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[85])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2974447 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2974447 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[981])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.16726526468004579152401897346480292056575974373527773081526841548673877465222
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    879551 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    879551 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    978551 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x90dc9d [100100001101110010011101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    978551 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x90dc9d [100100001101110010011101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])