SRAM_CTRL/MAIN Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.360s	6.355ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.580s	17.054us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.550s	27.447us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.130s	108.568us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.640s	24.269us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.110s	359.740us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.550s	27.447us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	24.269us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.791m	24.733ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.739m	48.848ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.879m	38.172ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.117m	16.166ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.588m	62.306ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.702m	28.038ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	41.130s	10.164ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.413m	15.826ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	45.750s	1.260ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.825m	20.739ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	15.450s	5.131ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	17.510s	2.894ms	1	1	100.00
		sram_ctrl_throughput_w_readback	12.680s	1.134ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.157m	14.524ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.520s	348.791us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	12.398m	128.674ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.640s	19.411us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.610s	669.713us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.610s	669.713us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.580s	17.054us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	27.447us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	24.269us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	14.752us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.580s	17.054us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	27.447us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	24.269us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	14.752us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	30.830s	14.355ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.550s	3.403us	0	1	0.00
		sram_ctrl_tl_intg_err	2.880s	398.640us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.550s	3.403us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.880s	398.640us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.157m	14.524ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.157m	14.524ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.550s	27.447us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.413m	15.826ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.413m	15.826ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.413m	15.826ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	41.130s	10.164ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.400s	1.560ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	30.830s	14.355ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.140s	660.041us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.360s	6.355ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.360s	6.355ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.413m	15.826ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.550s	3.403us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	41.130s	10.164ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.550s	3.403us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.550s	3.403us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.360s	6.355ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.550s	3.403us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	23.960s	3.746ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.46074932148098818233032079935212047334968713170767772414668866682177350709300
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 660040936 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x6c) != exp (0x4a)
        UVM_INFO @ 660040936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.39113096663443835215021655002217495923063331132470120532781585284500609016253
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3403361 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3403361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---