SRAM_CTRL/RET Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	5.160s	340.757us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.750s	14.892us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.550s	14.865us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.710s	769.454us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.800s	48.271us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.990s	133.890us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.550s	14.865us	1	1	100.00
		sram_ctrl_csr_aliasing	1.800s	48.271us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.310s	3.371ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.980s	837.041us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.641m	44.789ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.479m	1.317ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	53.150s	4.556ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.289m	3.417ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.430s	862.840us	1	1	100.00
V2	executable	sram_ctrl_executable	12.836m	39.828ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	22.960s	2.244ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.552m	177.230ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	20.240s	241.332us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	3.090s	49.942us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.024m	540.928us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.636m	48.683ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.810s	83.458us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	27.827m	12.133ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.520s	14.116us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.400s	20.699us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.400s	20.699us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.750s	14.892us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	14.865us	1	1	100.00
		sram_ctrl_csr_aliasing	1.800s	48.271us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	24.464us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.750s	14.892us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	14.865us	1	1	100.00
		sram_ctrl_csr_aliasing	1.800s	48.271us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	24.464us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.510s	814.907us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.550s	5.011us	0	1	0.00
		sram_ctrl_tl_intg_err	2.870s	644.440us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.550s	5.011us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.870s	644.440us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.636m	48.683ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.636m	48.683ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.550s	14.865us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.836m	39.828ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.836m	39.828ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.836m	39.828ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.430s	862.840us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.100s	83.201us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.510s	814.907us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.930s	79.094us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	5.160s	340.757us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	5.160s	340.757us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.836m	39.828ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.550s	5.011us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.430s	862.840us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.550s	5.011us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.550s	5.011us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	5.160s	340.757us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.550s	5.011us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.767m	1.921ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.48501301145651880828218769136561538962275014668617741241130344083042859007226
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   5010832 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   5010832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---