UART Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.520s	466.211us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.600s	13.973us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.510s	50.135us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.500s	115.561us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.660s	98.879us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.830s	25.101us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.510s	50.135us	1	1	100.00
		uart_csr_aliasing	1.660s	98.879us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.688m	57.540ms	1	1	100.00
V2	parity	uart_smoke	2.520s	466.211us	1	1	100.00
		uart_tx_rx	1.688m	57.540ms	1	1	100.00
V2	parity_error	uart_intr	5.590s	13.835ms	1	1	100.00
		uart_rx_parity_err	25.660s	64.085ms	1	1	100.00
V2	watermark	uart_tx_rx	1.688m	57.540ms	1	1	100.00
		uart_intr	5.590s	13.835ms	1	1	100.00
V2	fifo_full	uart_fifo_full	16.000s	45.026ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	3.233m	173.154ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	17.100s	8.457ms	1	1	100.00
V2	rx_frame_err	uart_intr	5.590s	13.835ms	1	1	100.00
V2	rx_break_err	uart_intr	5.590s	13.835ms	1	1	100.00
V2	rx_timeout	uart_intr	5.590s	13.835ms	1	1	100.00
V2	perf	uart_perf	1.469m	9.264ms	1	1	100.00
V2	sys_loopback	uart_loopback	11.830s	6.791ms	1	1	100.00
V2	line_loopback	uart_loopback	11.830s	6.791ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.744m	231.077ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	31.580s	26.506ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	18.900s	6.510ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	14.480s	2.325ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.514m	133.801ms	1	1	100.00
V2	stress_all	uart_stress_all	1.396m	467.921ms	1	1	100.00
V2	alert_test	uart_alert_test	1.480s	40.439us	1	1	100.00
V2	intr_test	uart_intr_test	1.750s	34.907us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.270s	71.329us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.270s	71.329us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.600s	13.973us	1	1	100.00
		uart_csr_rw	1.510s	50.135us	1	1	100.00
		uart_csr_aliasing	1.660s	98.879us	1	1	100.00
		uart_same_csr_outstanding	1.500s	28.882us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.600s	13.973us	1	1	100.00
		uart_csr_rw	1.510s	50.135us	1	1	100.00
		uart_csr_aliasing	1.660s	98.879us	1	1	100.00
		uart_same_csr_outstanding	1.500s	28.882us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.940s	123.278us	1	1	100.00
		uart_tl_intg_err	1.910s	271.124us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.910s	271.124us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	23.110s	2.637ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00