CHIP Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: `6f17fda`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.979m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.979m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.155m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.061m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.019m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.792m	5.543ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.792m	5.543ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.792m	5.543ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	2.689m		0	1	0.00
		chip_sw_example_manufacturer	35.439s		0	1	0.00
		chip_sw_example_concurrency	4.045m	4.094ms	1	1	100.00
		chip_sw_uart_smoketest_signed	17.901s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.930s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	11.490s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	11.490s		0	1	0.00
V1	xbar_smoke	xbar_smoke	15.780s	52.092us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.591m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.610m	8.019ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.218m	3.788ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	19.348s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.992s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	39.620s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	22.332s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.480s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.480s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.199m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.021m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.331m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.331m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.961m	5.540ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.823m	2.948ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.387m	7.308ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.439s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.212s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	11.281m	17.876ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.122m	6.297ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	23.407m	18.015ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	23.407m	18.015ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.534s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.540s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.540s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	12.307s		0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs	13.956s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.404m	5.546ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.026m	4.458ms	1	1	100.00
		chip_sw_aes_idle	4.181m	5.061ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.797m	4.932ms	1	1	100.00
		chip_sw_kmac_idle	3.953m	3.575ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.861s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.808s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.127s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.849s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.833s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.950s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.849s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.559s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.696s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.378s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.500s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.833s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.950s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.849s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.559s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.696s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.378s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.500s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.337s		0	1	0.00
		chip_sw_aes_enc_jitter_en	53.680s	10.280us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	47.270s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.220s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.088m	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.865s		0	1	0.00
		chip_sw_clkmgr_jitter	3.883m	4.634ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.880m	5.487ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.352s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	45.210s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	57.920s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	49.020s	10.180us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	55.400s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	48.300s	10.120us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.006s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.682s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.646s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.006s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	17.637m	17.227ms	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.431m	13.342ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	16.540s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.157s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.431m	13.342ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	16.634s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	13.666s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	20.269s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	15.992s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	27.567s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	17.637m	17.227ms	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.387m	7.308ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	18.904m	20.025ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.347m	10.514ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	25.814m	30.014ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.933m	3.941ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	17.637m	17.227ms	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	14.290s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.561s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	17.637m	17.227ms	0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs	13.956s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.809s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	25.814m	30.014ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.960s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.289s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.971s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.106s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.709s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	15.249s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.561s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.542s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	25.909s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.542s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.542s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.542s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.456m	20.010ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	21.244s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	21.855s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	16.322s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	23.698s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.542s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.077m	20.010ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.398m	14.622ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	15.224s		0	1	0.00
		chip_prim_tl_access	12.710m	23.981ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.833s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.950s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.849s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.559s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.696s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.378s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.500s		0	1	0.00
		chip_rv_dm_lc_disabled	11.281m	17.876ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.049m	4.771ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	53.680s	10.280us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.017m	3.765ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.181m	5.061ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.681m	3.936ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	47.270s	10.280us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.797m	4.932ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.627m	3.288ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.316m	3.926ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.088m	10.220us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.077m	20.010ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.542s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	38.440s	10.380us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.994m	4.218ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.953m	3.575ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.152s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.152s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.319s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.488m	5.934ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.582s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.077m	20.010ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.220s	10.280us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	12.266s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	18.337s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.026m	4.458ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.026m	4.458ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.026m	4.458ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.527m	4.397ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.398m	14.622ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.398m	14.622ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.510s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.865s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	15.224s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	17.637m	17.227ms	0	1	0.00
		chip_sw_data_integrity_escalation	2.331m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.542s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.527m	4.397ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.077m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	11.510s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	3.707m	5.104ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.527m	4.397ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.077m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	11.510s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	3.707m	5.104ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.542s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.098s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	25.909s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	21.244s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	21.855s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	16.322s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	23.698s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.542s		0	1	0.00
		chip_prim_tl_access	12.710m	23.981ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	12.710m	23.981ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.829s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.354s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.682s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.337s		0	1	0.00
		chip_sw_aes_enc_jitter_en	53.680s	10.280us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	47.270s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.220s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.088m	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.865s		0	1	0.00
		chip_sw_clkmgr_jitter	3.883m	4.634ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	9.633m	10.175ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	9.633m	10.175ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.612m	5.029ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.422m	5.009ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.053m	4.171ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.569m	7.158ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.006m	5.130ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.922m	4.202ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.707m	5.104ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	18.904m	20.025ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	18.904m	20.025ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.513m	4.660ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.547m	3.396ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.692m	4.355ms	1	1	100.00
		chip_sw_csrng_smoketest	3.076m	5.019ms	1	1	100.00
		chip_sw_gpio_smoketest	3.976m	5.512ms	1	1	100.00
		chip_sw_hmac_smoketest	4.160m	5.492ms	1	1	100.00
		chip_sw_kmac_smoketest	3.693m	4.473ms	1	1	100.00
		chip_sw_otbn_smoketest	5.193m	4.403ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.002m	4.041ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.973m	4.866ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.279m	6.348ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.713m	4.930ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.608m	3.630ms	1	1	100.00
		chip_sw_uart_smoketest	3.288m	4.404ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	16.844s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	17.901s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.591m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.856s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.957m	4.964ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.594m	6.093ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.086m	5.390ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.353m	4.281ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	17.777s		0	1	0.00
		chip_rv_dm_lc_disabled	11.281m	17.876ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.855s		0	1	0.00
		chip_sw_lc_walkthrough_prod	11.475s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	21.949s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.407s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	17.777s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	19.736s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.427s		0	1	0.00
		rom_volatile_raw_unlock	10.821s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	22.618s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.760m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.225m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.071m	3.339ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.071m	3.339ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	11.490s		0	1	0.00
		chip_same_csr_outstanding	9.480s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	11.490s		0	1	0.00
		chip_same_csr_outstanding	9.480s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	48.700s	50.607us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.850s	12.845us	1	1	100.00
		xbar_smoke_large_delays	4.232m	2.189ms	1	1	100.00
		xbar_smoke_slow_rsp	5.178m	1.995ms	1	1	100.00
		xbar_random_zero_delays	40.700s	32.935us	1	1	100.00
		xbar_random_large_delays	2.648m	1.357ms	1	1	100.00
		xbar_random_slow_rsp	26.111m	10.119ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	39.970s	28.658us	1	1	100.00
		xbar_error_and_unmapped_addr	1.538m	209.343us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	24.170s	65.404us	1	1	100.00
		xbar_error_and_unmapped_addr	1.538m	209.343us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.042m	522.876us	1	1	100.00
		xbar_access_same_device_slow_rsp	58.395m	23.754ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.333m	249.327us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	18.765m	2.852ms	1	1	100.00
		xbar_stress_all_with_error	1.093m	64.256us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	11.901m	585.503us	1	1	100.00
		xbar_stress_all_with_reset_error	13.682m	536.923us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.210s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.159s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.212s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.107s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.280s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.561s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.435s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.382s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.328s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.632s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.553s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.427s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.732s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	10.519s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.001s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.403s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.519s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.862s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.053s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.445s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.624s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.389s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.634s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.143s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.158s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	14.158s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.136s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.643s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.264s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.971s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.018s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.765s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.782s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.776s		0	1	0.00
		rom_e2e_asm_init_dev	11.807s		0	1	0.00
		rom_e2e_asm_init_prod	11.526s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.600s		0	1	0.00
		rom_e2e_asm_init_rma	12.183s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.243s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.473s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.319s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.467s		0	1	0.00
V2		TOTAL			65	206	31.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.095m	5.464ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.540m	3.146ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.918s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.393s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.246s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.993s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	17.637m	17.227ms	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	18.568s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.252m	17.237ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	10.695s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.002s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.918s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.393s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.246s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.018s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.473s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.343s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.246m		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	18.567m	13.215ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.372m	3.739ms	1	1	100.00
		chip_sw_dma_abort	3.756m	5.086ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.497s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.777s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.640s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.570s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.014s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.619s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.916s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.203s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.870s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.350s		0	1	0.00
		chip_sw_mbx_smoketest	4.215m	4.537ms	1	1	100.00
		TOTAL			73	246	29.67

Failure Buckets

Job returned non-zero exit code has 145 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.69471252868022280781557242834679708091408382961549803123282140311013682792794
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  DEBUG: /nightly/runs/opentitan/rules/autogen.bzl:452:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (a5df71)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (91f84c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 141.237s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.30101914683405267697395527077727929947229798055887998617322597496812893164372
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (83199c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 15.760s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.55437174370523321080570451427124424522321561663290286866732292524238709929937
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (88f4ea)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.763s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.78615813499911316971671683247862622746682625542890546447692176328221275420375
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (8dc338)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 121.720s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.2016774803602580288846518220559657151828372931631488541187490171937424122955
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (f1ad3b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 110.637s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 140 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.70783837036044220583398889984253009300230274105635050546379451568685228381135
    Line 410, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.67346231438269655335781542947049553527058473731735331769322485628875448193007
    Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.83330991482473638975493628847817914932462300002411643884939145741750542270063
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.97163554302975120300840644952347234803421238437249867549502688470223797528664
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.8300622531978166565225341112091980056833891721284459949270748553266086838223
    Line 408, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.34256724385778116133883741455364933742054370082810036672982527392374497054170
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.31782394611208441759303022972541673915646503903569850203000392644306751677301
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.81379497516291134516164174933634300295141526880708647910923461567980525522664
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 2 failures:
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.46617916931818209027302715338729029800805090346157107037143075105900024081737
    Line 481, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
  UVM_ERROR @ 20025.342364 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20025.342364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_irq has 1 failures.
  - 0.chip_sw_aon_timer_irq.109079494413107871537275487444941020188979914118809064123544088453333783152967
    Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
```
  UVM_ERROR @ 18014.774434 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18014.774434 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage * key has 2 failures:
- Test chip_sw_keymgr_dpe_key_derivation has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation.44325862943556753785700542764521145077469682316796314133957540943757739612624
    Line 446, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
```
  UVM_FATAL @ 20010.220001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_prod.72108882544972481332812998546438379913012176809914438500177757821383705671110
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 20010.100001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.85065665096073196544549626744611226585202653561295623010294772688004749412183
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 5540.368648 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h940910ec  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h1  a_user: 'h248dc  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5540.368648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.55747487405431099317248798475040117853380331795030091119325449419105438838294
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 2948.240087 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h7b9997ba  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h1  a_user: 'h2488d  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2948.240087 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.30102893746484406014019663842851729633486033593253876589958104694690627883091
    Line 447, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 17226.636394 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 17226.636394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.48804454160866489096124321837866352551056021841890876908737679330837972810548
    Line 486, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3788.313314 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3788.313314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.47863934263876735187992330539221178465762723668950249043589949943714521814928
    Line 517, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  UVM_ERROR @ 17236.581880 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 17236.581880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.95914573975353283374225136881555064367182156551352868382709525885936342269942
    Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 30014.488021 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 30000000 ns

  UVM_INFO @ 30014.488021 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.95476882658013912885393566324765768000337311582244141055452210653256385843960
    Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5028.654752 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5028.654752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.29717044777573439625665087183248002218733149894189856567284956179989843602431
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 7157.988392 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 7157.988392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.26291882148527280023443568117572353568493027343616309627712778046782860621849
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35774) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.42495724789730792998342975320896175325631849194552721821255801970307940118161
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3338.936196 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35774) { a_addr: 'h1460112  a_data: 'h40d23bf9  a_mask: 'h0  a_size: 'h0  a_param: 'h0  a_source: 'h2a  a_opcode: 'h4  a_user: 'h251e7  d_param: 'h0  d_source: 'h2a  d_data: 'h0  d_size: 'h0  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h4aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3338.936196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.75899232828946364757788900543281092861412495302821339066454772340768033345364
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.34272217530052321447569863572101178981998929734288188530943069834578971762005
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5086.189650 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5086.189650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```