CSRNG Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	17.961us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	33.697us	1	1	100.00
V1	csr_rw	csrng_csr_rw	5.000s	48.194us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	15.000s	266.320us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	69.899us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	62.360us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	48.194us	1	1	100.00
		csrng_csr_aliasing	7.000s	69.899us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	7.000s	137.373us	1	1	100.00
V2	alerts	csrng_alert	16.000s	413.053us	1	1	100.00
V2	err	csrng_err	5.000s	19.159us	1	1	100.00
V2	cmds	csrng_cmds	2.300m	11.908ms	1	1	100.00
V2	life cycle	csrng_cmds	2.300m	11.908ms	1	1	100.00
V2	stress_all	csrng_stress_all	2.367m	5.361ms	1	1	100.00
V2	intr_test	csrng_intr_test	5.000s	26.497us	1	1	100.00
V2	alert_test	csrng_alert_test	4.000s	16.506us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	6.000s	59.775us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	6.000s	59.775us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	33.697us	1	1	100.00
		csrng_csr_rw	5.000s	48.194us	1	1	100.00
		csrng_csr_aliasing	7.000s	69.899us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	105.922us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	33.697us	1	1	100.00
		csrng_csr_rw	5.000s	48.194us	1	1	100.00
		csrng_csr_aliasing	7.000s	69.899us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	105.922us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	tl_intg_err	csrng_sec_cm	6.000s	64.817us	1	1	100.00
		csrng_tl_intg_err	5.000s	46.795us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	20.258us	1	1	100.00
		csrng_csr_rw	5.000s	48.194us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	16.000s	413.053us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	2.367m	5.361ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
		csrng_sec_cm	6.000s	64.817us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
		csrng_sec_cm	6.000s	64.817us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
		csrng_sec_cm	6.000s	64.817us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
		csrng_sec_cm	6.000s	64.817us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
		csrng_sec_cm	6.000s	64.817us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
		csrng_sec_cm	6.000s	64.817us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
		csrng_sec_cm	6.000s	64.817us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	16.000s	413.053us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	2.367m	5.361ms	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	16.000s	413.053us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	5.000s	46.795us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
		csrng_sec_cm	6.000s	64.817us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
		csrng_sec_cm	6.000s	64.817us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	137.373us	1	1	100.00
		csrng_err	5.000s	19.159us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	56.000s	908.376us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:908) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 0.csrng_stress_all_with_rand_reset.59755963874891149928236864834625073324675186894249429193199306723933391549624
      Line 107, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 908375819 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 908375819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---