DMA Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	9.000s	1.468ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	2.403ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	371.259us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	16.452us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	58.411us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	8.000s	588.205us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	517.090us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	60.333us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	58.411us	1	1	100.00
		dma_csr_aliasing	9.000s	517.090us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	24.000s	7.063ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	28.700m	1.647s	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	6.117m	62.010ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	4.867m	27.745ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	28.700m	1.647s	1	1	100.00
V2	dma_abort	dma_abort	6.000s	328.033us	1	1	100.00
V2	dma_stress_all	dma_stress_all	48.000s	15.185ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	14.631us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	746.083us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	746.083us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	16.452us	1	1	100.00
		dma_csr_rw	4.000s	58.411us	1	1	100.00
		dma_csr_aliasing	9.000s	517.090us	1	1	100.00
		dma_same_csr_outstanding	4.000s	25.763us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	16.452us	1	1	100.00
		dma_csr_rw	4.000s	58.411us	1	1	100.00
		dma_csr_aliasing	9.000s	517.090us	1	1	100.00
		dma_same_csr_outstanding	4.000s	25.763us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	16.000s	166.713us	1	1	100.00
		dma_generic_stress	4.867m	27.745ms	1	1	100.00
		dma_handshake_stress	28.700m	1.647s	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	363.483us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.350m	8.208ms	1	1	100.00
		dma_longer_transfer	9.000s	1.068ms	1	1	100.00
		TOTAL			21	21	100.00