EDN Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.740s 40.107us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.590s 74.686us 1 1 100.00
V1 csr_rw edn_csr_rw 1.710s 18.691us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.330s 1.138ms 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.740s 32.649us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.130s 117.481us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.710s 18.691us 1 1 100.00
edn_csr_aliasing 1.740s 32.649us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.050s 68.930us 1 1 100.00
V2 csrng_commands edn_genbits 2.050s 68.930us 1 1 100.00
V2 genbits edn_genbits 2.050s 68.930us 1 1 100.00
V2 interrupts edn_intr 1.830s 65.927us 1 1 100.00
V2 alerts edn_alert 2.080s 52.083us 1 1 100.00
V2 errs edn_err 2.050s 19.186us 1 1 100.00
V2 disable edn_disable 1.800s 18.173us 1 1 100.00
edn_disable_auto_req_mode 1.980s 47.961us 1 1 100.00
V2 stress_all edn_stress_all 5.650s 376.907us 1 1 100.00
V2 intr_test edn_intr_test 1.540s 34.340us 1 1 100.00
V2 alert_test edn_alert_test 1.780s 25.975us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.450s 32.000us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.450s 32.000us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.590s 74.686us 1 1 100.00
edn_csr_rw 1.710s 18.691us 1 1 100.00
edn_csr_aliasing 1.740s 32.649us 1 1 100.00
edn_same_csr_outstanding 2.160s 41.221us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.590s 74.686us 1 1 100.00
edn_csr_rw 1.710s 18.691us 1 1 100.00
edn_csr_aliasing 1.740s 32.649us 1 1 100.00
edn_same_csr_outstanding 2.160s 41.221us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.540s 279.783us 1 1 100.00
edn_tl_intg_err 2.510s 468.271us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.600s 42.165us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.080s 52.083us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.540s 279.783us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.540s 279.783us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.540s 279.783us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.540s 279.783us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.080s 52.083us 1 1 100.00
edn_sec_cm 4.540s 279.783us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.080s 52.083us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.510s 468.271us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets