HMAC Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.510s 210.666us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 2.040s 22.634us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.890s 26.011us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.150s 2.344ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.710s 366.541us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.940s 73.899us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.890s 26.011us 1 1 100.00
hmac_csr_aliasing 4.710s 366.541us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 51.900s 5.807ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.920s 243.566us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.181m 45.003ms 1 1 100.00
hmac_test_sha384_vectors 21.000s 1.972ms 1 1 100.00
hmac_test_sha512_vectors 21.080s 498.687us 1 1 100.00
hmac_test_hmac256_vectors 12.390s 369.190us 1 1 100.00
hmac_test_hmac384_vectors 11.780s 298.830us 1 1 100.00
hmac_test_hmac512_vectors 7.860s 222.592us 1 1 100.00
V2 burst_wr hmac_burst_wr 21.080s 2.296ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.215m 2.562ms 1 1 100.00
V2 error hmac_error 39.750s 12.843ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 38.100s 2.051ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.510s 210.666us 1 1 100.00
hmac_long_msg 51.900s 5.807ms 1 1 100.00
hmac_back_pressure 1.920s 243.566us 1 1 100.00
hmac_datapath_stress 5.215m 2.562ms 1 1 100.00
hmac_burst_wr 21.080s 2.296ms 1 1 100.00
hmac_stress_all 8.170m 23.448ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.510s 210.666us 1 1 100.00
hmac_long_msg 51.900s 5.807ms 1 1 100.00
hmac_back_pressure 1.920s 243.566us 1 1 100.00
hmac_datapath_stress 5.215m 2.562ms 1 1 100.00
hmac_wipe_secret 38.100s 2.051ms 1 1 100.00
hmac_test_sha256_vectors 3.181m 45.003ms 1 1 100.00
hmac_test_sha384_vectors 21.000s 1.972ms 1 1 100.00
hmac_test_sha512_vectors 21.080s 498.687us 1 1 100.00
hmac_test_hmac256_vectors 12.390s 369.190us 1 1 100.00
hmac_test_hmac384_vectors 11.780s 298.830us 1 1 100.00
hmac_test_hmac512_vectors 7.860s 222.592us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.510s 210.666us 1 1 100.00
hmac_long_msg 51.900s 5.807ms 1 1 100.00
hmac_back_pressure 1.920s 243.566us 1 1 100.00
hmac_datapath_stress 5.215m 2.562ms 1 1 100.00
hmac_burst_wr 21.080s 2.296ms 1 1 100.00
hmac_error 39.750s 12.843ms 1 1 100.00
hmac_wipe_secret 38.100s 2.051ms 1 1 100.00
hmac_test_sha256_vectors 3.181m 45.003ms 1 1 100.00
hmac_test_sha384_vectors 21.000s 1.972ms 1 1 100.00
hmac_test_sha512_vectors 21.080s 498.687us 1 1 100.00
hmac_test_hmac256_vectors 12.390s 369.190us 1 1 100.00
hmac_test_hmac384_vectors 11.780s 298.830us 1 1 100.00
hmac_test_hmac512_vectors 7.860s 222.592us 1 1 100.00
hmac_stress_all 8.170m 23.448ms 1 1 100.00
V2 stress_all hmac_stress_all 8.170m 23.448ms 1 1 100.00
V2 alert_test hmac_alert_test 1.590s 13.874us 1 1 100.00
V2 intr_test hmac_intr_test 1.510s 17.714us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.430s 50.479us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.430s 50.479us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 2.040s 22.634us 1 1 100.00
hmac_csr_rw 1.890s 26.011us 1 1 100.00
hmac_csr_aliasing 4.710s 366.541us 1 1 100.00
hmac_same_csr_outstanding 2.540s 197.424us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 2.040s 22.634us 1 1 100.00
hmac_csr_rw 1.890s 26.011us 1 1 100.00
hmac_csr_aliasing 4.710s 366.541us 1 1 100.00
hmac_same_csr_outstanding 2.540s 197.424us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.970s 173.753us 1 1 100.00
hmac_tl_intg_err 3.500s 180.835us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.500s 180.835us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.510s 210.666us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.980s 166.985us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 23.330s 7.249ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.830s 1.899ms 1 1 100.00
TOTAL 28 28 100.00