I2C Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	39.040s	1.249ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	13.170s	12.274ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.550s	23.056us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.750s	37.616us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.480s	219.064us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.910s	42.675us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.960s	37.028us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.750s	37.616us	1	1	100.00
		i2c_csr_aliasing	2.910s	42.675us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.070s	401.027us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	4.747m	64.018ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	4.600s	444.389us	1	1	100.00
V2	host_override	i2c_host_override	1.650s	290.192us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.042m	4.696ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	34.390s	3.590ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.820s	165.097us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.140s	324.407us	1	1	100.00
		i2c_host_fifo_reset_rx	6.730s	174.780us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	33.130s	4.170ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	16.910s	766.402us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.570s	482.043us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.000s	3.498ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	48.050s	46.309ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.910s	1.608ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	17.300s	560.119us	1	1	100.00
		i2c_target_intr_smoke	5.040s	6.249ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.870s	347.309us	1	1	100.00
		i2c_target_fifo_reset_tx	2.190s	305.239us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.552m	29.542ms	1	1	100.00
		i2c_target_stress_rd	17.300s	560.119us	1	1	100.00
		i2c_target_intr_stress_wr	14.940s	2.809ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.530s	4.988ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	19.610s	3.824ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.680s	1.406ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	9.490s	10.262ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.280s	768.219us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.080s	836.347us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.600s	444.389us	1	1	100.00
		i2c_host_perf_precise	2.250s	230.565us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	16.910s	766.402us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.340s	210.766us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.810s	1.940ms	1	1	100.00
		i2c_target_nack_acqfull_addr	3.470s	537.176us	1	1	100.00
		i2c_target_nack_txstretch	2.170s	183.575us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.170s	435.697us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.320s	953.179us	1	1	100.00
V2	alert_test	i2c_alert_test	1.550s	27.110us	1	1	100.00
V2	intr_test	i2c_intr_test	1.580s	26.245us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.490s	358.909us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.490s	358.909us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.550s	23.056us	1	1	100.00
		i2c_csr_rw	1.750s	37.616us	1	1	100.00
		i2c_csr_aliasing	2.910s	42.675us	1	1	100.00
		i2c_same_csr_outstanding	1.890s	219.094us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.550s	23.056us	1	1	100.00
		i2c_csr_rw	1.750s	37.616us	1	1	100.00
		i2c_csr_aliasing	2.910s	42.675us	1	1	100.00
		i2c_same_csr_outstanding	1.890s	219.094us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.870s	508.881us	1	1	100.00
		i2c_sec_cm	1.730s	44.892us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.870s	508.881us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	36.530s	1.056ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.060s	250.547us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	5.550s	1.968ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.45569970695723555911776703240134645437145126743831005464782988545843714011596
      Line 202, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 64018389722 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @8695016
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.9811203466385095867186372006491931275861320281672508095163382561571067622633
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 250547068 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 250547068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.108026647380784736366937607392331184558969679587512029127465261075620338027515
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10261703717 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10261703717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.84943108766580767244780150753540547359655438326926773476593093608225062169785
      Line 102, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1056221518 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1056221518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:811) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.72075747517448191900569347995518471444645750522828342927516216043437893964310
      Line 112, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1967945494 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1967945494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.99853138418225319884652239186877562877474434258332313772363543642172218074509
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 183575476 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 183575476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---