KEYMGR Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	5.300s	758.426us	1	1	100.00
V1	random	keymgr_random	21.000s	1.110ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.810s	55.666us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.960s	50.629us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	4.670s	383.729us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	4.030s	193.466us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.400s	294.381us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.960s	50.629us	1	1	100.00
		keymgr_csr_aliasing	4.030s	193.466us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	4.510s	97.571us	1	1	100.00
V2	sideload	keymgr_sideload	4.190s	164.246us	1	1	100.00
		keymgr_sideload_kmac	2.550s	74.700us	1	1	100.00
		keymgr_sideload_aes	2.790s	100.161us	1	1	100.00
		keymgr_sideload_otbn	3.550s	105.513us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.000s	274.475us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.690s	143.352us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.130s	403.844us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.860s	97.190us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.710s	50.711us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.810s	232.353us	1	1	100.00
V2	stress_all	keymgr_stress_all	14.420s	675.630us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.760s	19.074us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.550s	17.839us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.560s	116.475us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.560s	116.475us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.810s	55.666us	1	1	100.00
		keymgr_csr_rw	1.960s	50.629us	1	1	100.00
		keymgr_csr_aliasing	4.030s	193.466us	1	1	100.00
		keymgr_same_csr_outstanding	3.490s	87.494us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.810s	55.666us	1	1	100.00
		keymgr_csr_rw	1.960s	50.629us	1	1	100.00
		keymgr_csr_aliasing	4.030s	193.466us	1	1	100.00
		keymgr_same_csr_outstanding	3.490s	87.494us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
		keymgr_tl_intg_err	1.790s	8.239us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.620s	116.485us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.620s	116.485us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.620s	116.485us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.620s	116.485us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	8.030s	1.926ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.790s	8.239us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.620s	116.485us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.510s	97.571us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	21.000s	1.110ms	1	1	100.00
		keymgr_csr_rw	1.960s	50.629us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	21.000s	1.110ms	1	1	100.00
		keymgr_csr_rw	1.960s	50.629us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	21.000s	1.110ms	1	1	100.00
		keymgr_csr_rw	1.960s	50.629us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.690s	143.352us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.710s	50.711us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.710s	50.711us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	21.000s	1.110ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.530s	133.736us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.130s	79.036us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.690s	143.352us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.130s	79.036us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.130s	79.036us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.130s	79.036us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.400s	2.086ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.130s	79.036us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	4.700s	1.975ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.8103274927060734387117040970850942189380099356421130206691285872894671669294
      Line 83, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
        UVM_ERROR @   8238934 ps: (keymgr_csr_assert_fpv.sv:396) [ASSERT FAILED] sealing_sw_binding_1_rd_A
        UVM_INFO @   8238934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.29982435611395661513317446668632051769740928490447483737524929678669329400750
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
        UVM_ERROR @ 383728522 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] sealing_sw_binding_7_rd_A
        UVM_INFO @ 383728522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:907) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.82841259761197820156079271479073541877100928030973336287519814880321877309390
      Line 639, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1975033501 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1975033501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---