KMAC/MASKED Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 40.050s 4.174ms 1 1 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.960s 28.333us 1 1 100.00
V1 csr_rw kmac_csr_rw 1.870s 68.213us 1 1 100.00
V1 csr_bit_bash kmac_csr_bit_bash 16.470s 20.547ms 1 1 100.00
V1 csr_aliasing kmac_csr_aliasing 5.020s 1.533ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.130s 41.938us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.870s 68.213us 1 1 100.00
kmac_csr_aliasing 5.020s 1.533ms 1 1 100.00
V1 mem_walk kmac_mem_walk 1.730s 28.816us 1 1 100.00
V1 mem_partial_access kmac_mem_partial_access 2.320s 69.318us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 long_msg_and_output kmac_long_msg_and_output 37.375m 332.554ms 1 1 100.00
V2 burst_write kmac_burst_write 18.373m 181.996ms 1 1 100.00
V2 test_vectors kmac_test_vectors_sha3_224 37.980s 10.964ms 1 1 100.00
kmac_test_vectors_sha3_256 30.601m 344.367ms 1 1 100.00
kmac_test_vectors_sha3_384 20.810s 6.065ms 1 1 100.00
kmac_test_vectors_sha3_512 18.564m 48.180ms 1 1 100.00
kmac_test_vectors_shake_128 2.011m 14.329ms 1 1 100.00
kmac_test_vectors_shake_256 29.825m 420.238ms 1 1 100.00
kmac_test_vectors_kmac 4.370s 983.828us 1 1 100.00
kmac_test_vectors_kmac_xof 4.200s 99.517us 1 1 100.00
V2 sideload kmac_sideload 5.468m 5.580ms 1 1 100.00
V2 app kmac_app 2.362m 6.723ms 1 1 100.00
V2 app_with_partial_data kmac_app_with_partial_data 2.771m 5.669ms 1 1 100.00
V2 entropy_refresh kmac_entropy_refresh 17.780s 3.550ms 1 1 100.00
V2 error kmac_error 3.606m 15.296ms 1 1 100.00
V2 key_error kmac_key_error 8.930s 1.433ms 1 1 100.00
V2 sideload_invalid kmac_sideload_invalid 4.350s 452.612us 1 1 100.00
V2 edn_timeout_error kmac_edn_timeout_error 36.130s 1.620ms 1 1 100.00
V2 entropy_mode_error kmac_entropy_mode_error 2.000s 27.611us 1 1 100.00
V2 entropy_ready_error kmac_entropy_ready_error 26.480s 3.076ms 1 1 100.00
V2 lc_escalation kmac_lc_escalation 2.600s 86.283us 1 1 100.00
V2 stress_all kmac_stress_all 11.904m 12.036ms 1 1 100.00
V2 intr_test kmac_intr_test 1.690s 13.729us 1 1 100.00
V2 alert_test kmac_alert_test 1.570s 14.176us 1 1 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 2.750s 130.366us 1 1 100.00
V2 tl_d_illegal_access kmac_tl_errors 2.750s 130.366us 1 1 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.960s 28.333us 1 1 100.00
kmac_csr_rw 1.870s 68.213us 1 1 100.00
kmac_csr_aliasing 5.020s 1.533ms 1 1 100.00
kmac_same_csr_outstanding 3.230s 1.199ms 1 1 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.960s 28.333us 1 1 100.00
kmac_csr_rw 1.870s 68.213us 1 1 100.00
kmac_csr_aliasing 5.020s 1.533ms 1 1 100.00
kmac_same_csr_outstanding 3.230s 1.199ms 1 1 100.00
V2 TOTAL 26 26 100.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 2.080s 219.408us 1 1 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 2.080s 219.408us 1 1 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 2.080s 219.408us 1 1 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 2.080s 219.408us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 2.980s 128.484us 1 1 100.00
V2S tl_intg_err kmac_sec_cm 44.610s 5.000ms 1 1 100.00
kmac_tl_intg_err 2.620s 59.375us 1 1 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 2.620s 59.375us 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 2.600s 86.283us 1 1 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 40.050s 4.174ms 1 1 100.00
V2S sec_cm_key_sideload kmac_sideload 5.468m 5.580ms 1 1 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 2.080s 219.408us 1 1 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 44.610s 5.000ms 1 1 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 44.610s 5.000ms 1 1 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 44.610s 5.000ms 1 1 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 40.050s 4.174ms 1 1 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 2.600s 86.283us 1 1 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 44.610s 5.000ms 1 1 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 4.364m 5.465ms 1 1 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 40.050s 4.174ms 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 33.010s 1.706ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 40 40 100.00