KMAC/UNMASKED Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	30.720s	3.646ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.760s	43.161us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.050s	28.347us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.730s	1.006ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.160s	202.522us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.340s	430.285us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.050s	28.347us	1	1	100.00
		kmac_csr_aliasing	4.160s	202.522us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.650s	32.796us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.040s	60.840us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	33.665m	421.098ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.909m	15.578ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	25.158m	208.818ms	1	1	100.00
		kmac_test_vectors_sha3_256	21.366m	54.895ms	1	1	100.00
		kmac_test_vectors_sha3_384	17.952m	97.332ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.480s	4.342ms	1	1	100.00
		kmac_test_vectors_shake_128	22.136m	20.656ms	1	1	100.00
		kmac_test_vectors_shake_256	3.888m	64.195ms	1	1	100.00
		kmac_test_vectors_kmac	3.410s	488.431us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.410s	107.504us	1	1	100.00
V2	sideload	kmac_sideload	35.350s	7.156ms	1	1	100.00
V2	app	kmac_app	1.079m	2.298ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	53.550s	11.263ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	54.730s	10.097ms	1	1	100.00
V2	error	kmac_error	2.837m	16.187ms	1	1	100.00
V2	key_error	kmac_key_error	4.590s	415.152us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	58.440s	10.287ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	4.480s	108.599us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	14.530s	1.018ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	30.020s	4.054ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.300s	467.594us	1	1	100.00
V2	stress_all	kmac_stress_all	10.820m	193.337ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.470s	51.846us	1	1	100.00
V2	alert_test	kmac_alert_test	1.660s	24.768us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.680s	138.803us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.680s	138.803us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.760s	43.161us	1	1	100.00
		kmac_csr_rw	2.050s	28.347us	1	1	100.00
		kmac_csr_aliasing	4.160s	202.522us	1	1	100.00
		kmac_same_csr_outstanding	2.700s	93.666us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.760s	43.161us	1	1	100.00
		kmac_csr_rw	2.050s	28.347us	1	1	100.00
		kmac_csr_aliasing	4.160s	202.522us	1	1	100.00
		kmac_same_csr_outstanding	2.700s	93.666us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.030s	58.730us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.030s	58.730us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.030s	58.730us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.030s	58.730us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.760s	346.240us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	49.070s	23.304ms	1	1	100.00
		kmac_tl_intg_err	2.750s	65.326us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.750s	65.326us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.300s	467.594us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	30.720s	3.646ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	35.350s	7.156ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.030s	58.730us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	49.070s	23.304ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	49.070s	23.304ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	49.070s	23.304ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	30.720s	3.646ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.300s	467.594us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	49.070s	23.304ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.613m	45.612ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	30.720s	3.646ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.547m	49.718ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.20818411313065398734911501693914144481821585422284473118588881754423746588038
      Line 98, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10287149370 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5c5b5000, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
        UVM_INFO @ 10287149370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:907) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.108150762625722337014926429243691133681999201796854708242970881717587530567627
      Line 212, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 49717623550 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 49717623550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---