OTBN Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	180.880us	1	1	100.00
V1	single_binary	otbn_single	9.000s	36.696us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	11.882us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	34.706us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	379.854us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	41.234us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	351.787us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	34.706us	1	1	100.00
		otbn_csr_aliasing	6.000s	41.234us	1	1	100.00
V1	mem_walk	otbn_mem_walk	17.000s	2.996ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	12.000s	189.466us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	18.000s	207.351us	1	1	100.00
V2	multi_error	otbn_multi_err	1.083m	293.419us	1	1	100.00
V2	back_to_back	otbn_multi	2.033m	713.575us	1	1	100.00
V2	stress_all	otbn_stress_all	1.283m	276.724us	1	1	100.00
V2	lc_escalation	otbn_escalate	7.000s	40.503us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	25.464us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	13.000s	223.598us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	44.460us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	12.773us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	882.150us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	882.150us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	11.882us	1	1	100.00
		otbn_csr_rw	6.000s	34.706us	1	1	100.00
		otbn_csr_aliasing	6.000s	41.234us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	78.477us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	11.882us	1	1	100.00
		otbn_csr_rw	6.000s	34.706us	1	1	100.00
		otbn_csr_aliasing	6.000s	41.234us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	78.477us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	34.438us	1	1	100.00
		otbn_dmem_err	9.000s	20.071us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	106.596us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	32.988us	1	1	100.00
		otbn_mac_bignum_acc_err	9.000s	30.612us	1	1	100.00
		otbn_urnd_err	7.000s	24.692us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	48.524us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	24.556us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	23.115us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	3.650m	1.764ms	1	1	100.00
		otbn_tl_intg_err	18.000s	1.315ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	25.000s	702.959us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	180.880us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	20.071us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	34.438us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	18.000s	1.315ms	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	7.000s	40.503us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	34.438us	1	1	100.00
		otbn_dmem_err	9.000s	20.071us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	25.464us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	48.524us	1	1	100.00
		otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	36.696us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	34.438us	1	1	100.00
		otbn_dmem_err	9.000s	20.071us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	25.464us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	48.524us	1	1	100.00
		otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	7.000s	40.503us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	34.438us	1	1	100.00
		otbn_dmem_err	9.000s	20.071us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	25.464us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	48.524us	1	1	100.00
		otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	36.696us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	33.154us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	39.448us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	18.000s	115.149us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	18.000s	115.149us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	41.870us	0	1	0.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	63.201us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	86.728us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	86.728us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	10.124us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	36.696us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	36.696us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	36.696us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.033m	713.575us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	36.696us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	36.696us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	70.174us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	36.696us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.650m	1.764ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.333m	4.599ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			40	41	97.56

Failure Buckets

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
  • Test otbn_rf_base_intg_err has 1 failures.

    • 0.otbn_rf_base_intg_err.56924169918971011506770096764602886912907022968420141795323452056998795562214
      Line 108, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log

        UVM_ERROR @  41870473 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @  41870473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---