ROM_CTRL/32KB Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.990s	311.417us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.690s	733.256us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.090s	170.848us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.330s	385.245us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.270s	557.563us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.270s	596.012us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.090s	170.848us	1	1	100.00
		rom_ctrl_csr_aliasing	4.270s	557.563us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	4.330s	498.344us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.690s	555.375us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.140s	566.558us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	16.100s	593.555us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	6.830s	740.932us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	4.510s	533.722us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	8.590s	180.289us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	8.590s	180.289us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.690s	733.256us	1	1	100.00
		rom_ctrl_csr_rw	5.090s	170.848us	1	1	100.00
		rom_ctrl_csr_aliasing	4.270s	557.563us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.450s	1.072ms	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.690s	733.256us	1	1	100.00
		rom_ctrl_csr_rw	5.090s	170.848us	1	1	100.00
		rom_ctrl_csr_aliasing	4.270s	557.563us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.450s	1.072ms	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	21.130s	2.303ms	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	20.130s	1.610ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.005m	3.905ms	1	1	100.00
		rom_ctrl_tl_intg_err	38.410s	967.087us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.005m	3.905ms	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.005m	3.905ms	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.130s	2.303ms	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.130s	2.303ms	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	21.130s	2.303ms	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.130s	2.303ms	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.130s	2.303ms	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.005m	3.905ms	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.005m	3.905ms	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.990s	311.417us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.990s	311.417us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.990s	311.417us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	38.410s	967.087us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	21.130s	2.303ms	0	1	0.00
		rom_ctrl_kmac_err_chk	6.830s	740.932us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	21.130s	2.303ms	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.130s	2.303ms	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	21.130s	2.303ms	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	20.130s	1.610ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.005m	3.905ms	1	1	100.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.071m	9.189ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.83859739867690677723320272617983678146568860320198011085590720995079063887726
      Line 88, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 2302629198 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 2302629198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---