ROM_CTRL/64KB Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.350s 402.205us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.800s 299.729us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.880s 377.047us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.330s 537.448us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.670s 725.708us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 9.250s 1.203ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.880s 377.047us 1 1 100.00
rom_ctrl_csr_aliasing 5.670s 725.708us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.630s 1.060ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.490s 372.846us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 9.830s 1.316ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 19.380s 1.104ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 15.990s 2.024ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.760s 1.024ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.900s 1.495ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.900s 1.495ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.800s 299.729us 1 1 100.00
rom_ctrl_csr_rw 6.880s 377.047us 1 1 100.00
rom_ctrl_csr_aliasing 5.670s 725.708us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.120s 2.007ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.800s 299.729us 1 1 100.00
rom_ctrl_csr_rw 6.880s 377.047us 1 1 100.00
rom_ctrl_csr_aliasing 5.670s 725.708us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.120s 2.007ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.571m 13.267ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.190s 2.152ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.642m 1.787ms 1 1 100.00
rom_ctrl_tl_intg_err 1.172m 6.513ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.642m 1.787ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.642m 1.787ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.571m 13.267ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.571m 13.267ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.571m 13.267ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.571m 13.267ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.571m 13.267ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.642m 1.787ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.642m 1.787ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.350s 402.205us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.350s 402.205us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.350s 402.205us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.172m 6.513ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.571m 13.267ms 1 1 100.00
rom_ctrl_kmac_err_chk 15.990s 2.024ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.571m 13.267ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.571m 13.267ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.571m 13.267ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.190s 2.152ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.642m 1.787ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.450m 3.164ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00