SPI_DEVICE/1R1W Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.593m	586.720ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.910s	64.508us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.910s	670.997us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.740s	6.435ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	13.980s	1.259ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.360s	457.904us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.910s	670.997us	1	1	100.00
		spi_device_csr_aliasing	13.980s	1.259ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.780s	18.412us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.230s	48.066us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.760s	23.625us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.530s	1.447us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.700s	4.123us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.330s	64.748us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.330s	64.748us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	10.810s	47.651ms	1	1	100.00
		spi_device_tpm_sts_read	1.590s	76.263us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	13.340s	3.485ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.230s	2.108ms	1	1	100.00
		spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.180s	5.039ms	1	1	100.00
		spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.180s	5.039ms	1	1	100.00
		spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.280s	1.104ms	1	1	100.00
		spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.280s	1.104ms	1	1	100.00
		spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.280s	1.104ms	1	1	100.00
		spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.280s	1.104ms	1	1	100.00
		spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.280s	1.104ms	1	1	100.00
		spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.660s	408.716us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.670s	217.188us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.670s	217.188us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.670s	217.188us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	10.360s	557.989us	1	1	100.00
		spi_device_read_buffer_direct	3.050s	1.124ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.670s	217.188us	1	1	100.00
		spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	36.130s	21.687ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.610s	405.165us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.610s	405.165us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.593m	586.720ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.071m	9.113ms	1	1	100.00
V2	stress_all	spi_device_stress_all	50.630s	19.285ms	1	1	100.00
V2	alert_test	spi_device_alert_test	2.070s	14.721us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.680s	71.894us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.450s	254.942us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.450s	254.942us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.910s	64.508us	1	1	100.00
		spi_device_csr_rw	1.910s	670.997us	1	1	100.00
		spi_device_csr_aliasing	13.980s	1.259ms	1	1	100.00
		spi_device_same_csr_outstanding	2.440s	29.576us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.910s	64.508us	1	1	100.00
		spi_device_csr_rw	1.910s	670.997us	1	1	100.00
		spi_device_csr_aliasing	13.980s	1.259ms	1	1	100.00
		spi_device_same_csr_outstanding	2.440s	29.576us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.430s	60.251us	1	1	100.00
		spi_device_tl_intg_err	15.000s	304.155us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	15.000s	304.155us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	30.420s	8.322ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.50334894906832262541484276429952924126471548795013553963395495564178095684166
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    842518 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[9])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    842518 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    842518 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[905])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.100744926062515929791035605846927056386711652613849161869073856703821375090349
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3638904 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3638904 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   3642904 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd30d0e [110100110000110100001110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   3642904 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xd30d0e [110100110000110100001110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])