SPI_HOST Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	17.000s	5.884ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	64.583us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	60.383us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	64.063us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	22.797us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	25.161us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	60.383us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.797us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	158.763us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	20.155us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	88.792us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	8.000s	286.647us	1	1	100.00
		spi_host_error_cmd	4.000s	56.545us	1	1	100.00
		spi_host_event	18.000s	5.919ms	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	135.107us	1	1	100.00
V2	speed	spi_host_speed	5.000s	135.107us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	135.107us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	6.000s	122.060us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	1.010ms	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	135.107us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	135.107us	1	1	100.00
V2	duplex	spi_host_smoke	17.000s	5.884ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	17.000s	5.884ms	1	1	100.00
V2	stress_all	spi_host_stress_all	8.000s	349.112us	1	1	100.00
V2	spien	spi_host_spien	3.100m	6.585ms	1	1	100.00
V2	stall	spi_host_status_stall	37.000s	7.543ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	18.000s	4.974ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	8.000s	286.647us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	15.391us	1	1	100.00
V2	intr_test	spi_host_intr_test	5.000s	36.131us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	56.702us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	56.702us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	64.583us	1	1	100.00
		spi_host_csr_rw	4.000s	60.383us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.797us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	51.931us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	64.583us	1	1	100.00
		spi_host_csr_rw	4.000s	60.383us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.797us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	51.931us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	402.941us	1	1	100.00
		spi_host_sec_cm	4.000s	255.509us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	402.941us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	32.400m	100.001ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.102289632776510299260763234674884926244454132741939599895645046638813662664795
      Line 137, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100001409612 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf1e6d3d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100001409612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---