SRAM_CTRL/MAIN Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	4.170s	835.755us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.500s	36.484us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.610s	31.378us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.260s	45.053us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.590s	63.948us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.010s	351.008us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.610s	31.378us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	63.948us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.551m	14.129ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.753m	17.569ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	11.220m	85.219ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.732m	15.096ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	16.453m	40.819ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.893m	38.063ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	25.170s	36.353ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.357m	1.306ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.950s	4.456ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.020m	30.413ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	26.920s	772.216us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	14.560s	5.521ms	1	1	100.00
		sram_ctrl_throughput_w_readback	4.900s	712.232us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.486m	20.597ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.020s	364.071us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	34.408m	43.476ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.620s	45.361us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.340s	61.356us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.340s	61.356us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.500s	36.484us	1	1	100.00
		sram_ctrl_csr_rw	1.610s	31.378us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	63.948us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.430s	14.629us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.500s	36.484us	1	1	100.00
		sram_ctrl_csr_rw	1.610s	31.378us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	63.948us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.430s	14.629us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	22.100s	61.589ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.520s	1.768us	0	1	0.00
		sram_ctrl_tl_intg_err	2.230s	149.888us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.520s	1.768us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.230s	149.888us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.486m	20.597ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.486m	20.597ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.610s	31.378us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.357m	1.306ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.357m	1.306ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.357m	1.306ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	25.170s	36.353ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.540s	718.687us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	22.100s	61.589ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.760s	2.638ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	4.170s	835.755us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	4.170s	835.755us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.357m	1.306ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.520s	1.768us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	25.170s	36.353ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.520s	1.768us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.520s	1.768us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	4.170s	835.755us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.520s	1.768us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.240s	358.294us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.20991338742414834125707389095607788544835946743071744373329059189833904255948
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1768134 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1768134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---