SRAM_CTRL/RET Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	34.980s	1.462ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.640s	41.622us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.660s	23.444us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.980s	484.040us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.400s	20.977us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.830s	114.234us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.660s	23.444us	1	1	100.00
		sram_ctrl_csr_aliasing	1.400s	20.977us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.170s	943.858us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.960s	791.322us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.063m	5.954ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.397m	2.129ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	38.270s	2.617ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.844m	15.039ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.370s	375.894us	1	1	100.00
V2	executable	sram_ctrl_executable	3.532m	13.249ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	4.050s	56.088us	1	1	100.00
		sram_ctrl_partial_access_b2b	5.345m	17.868ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.690s	154.284us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	35.740s	592.325us	1	1	100.00
		sram_ctrl_throughput_w_readback	9.090s	138.198us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.794m	35.103ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.750s	186.272us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	27.299m	82.054ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.540s	18.155us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.870s	185.229us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.870s	185.229us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.640s	41.622us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	23.444us	1	1	100.00
		sram_ctrl_csr_aliasing	1.400s	20.977us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.570s	112.641us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.640s	41.622us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	23.444us	1	1	100.00
		sram_ctrl_csr_aliasing	1.400s	20.977us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.570s	112.641us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.210s	400.076us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.450s	4.025us	0	1	0.00
		sram_ctrl_tl_intg_err	2.150s	149.053us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.450s	4.025us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.150s	149.053us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.794m	35.103ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.794m	35.103ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.660s	23.444us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.532m	13.249ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.532m	13.249ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.532m	13.249ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.370s	375.894us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.560s	75.584us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.210s	400.076us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.630s	36.842us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	34.980s	1.462ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	34.980s	1.462ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.532m	13.249ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.450s	4.025us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.370s	375.894us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.450s	4.025us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.450s	4.025us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	34.980s	1.462ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.450s	4.025us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.248m	13.678ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.60346781058567932239932964630551937303938158006327133491188707673988423767651
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4024614 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4024614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---