UART Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.940s	496.737us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.700s	12.972us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.510s	31.260us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.180s	924.469us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.560s	39.231us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.930s	114.904us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.510s	31.260us	1	1	100.00
		uart_csr_aliasing	1.560s	39.231us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	16.770s	27.517ms	1	1	100.00
V2	parity	uart_smoke	2.940s	496.737us	1	1	100.00
		uart_tx_rx	16.770s	27.517ms	1	1	100.00
V2	parity_error	uart_intr	1.289m	163.740ms	1	1	100.00
		uart_rx_parity_err	1.441m	133.742ms	1	1	100.00
V2	watermark	uart_tx_rx	16.770s	27.517ms	1	1	100.00
		uart_intr	1.289m	163.740ms	1	1	100.00
V2	fifo_full	uart_fifo_full	35.750s	44.953ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	16.150s	25.831ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	11.910s	108.763ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.289m	163.740ms	1	1	100.00
V2	rx_break_err	uart_intr	1.289m	163.740ms	1	1	100.00
V2	rx_timeout	uart_intr	1.289m	163.740ms	1	1	100.00
V2	perf	uart_perf	59.660s	6.753ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.010s	272.893us	1	1	100.00
V2	line_loopback	uart_loopback	2.010s	272.893us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.524m	125.929ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	40.070s	40.994ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	8.170s	8.930ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	6.600s	5.522ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.002m	181.699ms	1	1	100.00
V2	stress_all	uart_stress_all	47.990s	93.294ms	1	1	100.00
V2	alert_test	uart_alert_test	1.450s	12.679us	1	1	100.00
V2	intr_test	uart_intr_test	1.610s	51.322us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.300s	189.538us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.300s	189.538us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.700s	12.972us	1	1	100.00
		uart_csr_rw	1.510s	31.260us	1	1	100.00
		uart_csr_aliasing	1.560s	39.231us	1	1	100.00
		uart_same_csr_outstanding	1.670s	15.776us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.700s	12.972us	1	1	100.00
		uart_csr_rw	1.510s	31.260us	1	1	100.00
		uart_csr_aliasing	1.560s	39.231us	1	1	100.00
		uart_same_csr_outstanding	1.670s	15.776us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.810s	304.125us	1	1	100.00
		uart_tl_intg_err	1.880s	185.204us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.880s	185.204us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	38.600s	16.210ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00