CHIP Simulation Results

Wednesday April 09 2025 17:04:44 UTC

GitHub Revision: `96c9c77`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	24.936s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	24.936s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.181m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.122m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	46.538s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.252m	6.294ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.252m	6.294ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.252m	6.294ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.554m		0	1	0.00
		chip_sw_example_manufacturer	2.760m		0	1	0.00
		chip_sw_example_concurrency	3.424m	3.970ms	1	1	100.00
		chip_sw_uart_smoketest_signed	18.143s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.620s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	16.120s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	16.120s		0	1	0.00
V1	xbar_smoke	xbar_smoke	17.440s	56.793us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	12.983s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.185m	7.705ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.993m	3.737ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	13.415s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	13.069s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	11.645s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	27.187s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.220s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.220s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.890m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	26.139s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.312m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.312m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.645m	4.601ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.629m	5.367ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.465m	8.524ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.672s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.075s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	18.483m	29.295ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.075m	5.915ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.782m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.782m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.423s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.340s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.340s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.621s		0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs	12.798s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.608m	5.684ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.970m	5.636ms	1	1	100.00
		chip_sw_aes_idle	4.464m	3.251ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.069m	4.183ms	1	1	100.00
		chip_sw_kmac_idle	3.593m	5.050ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.681s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.382s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.947s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.221s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.582s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.073s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.654s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.933s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.874s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.949s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.512s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.582s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.073s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.654s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.933s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.874s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.949s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.512s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.120s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.940s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	45.140s	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	54.550s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	50.990s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.553s		0	1	0.00
		chip_sw_clkmgr_jitter	4.031m	4.919ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.972m	3.490ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.807s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	52.150s	10.280us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	49.250s	10.160us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	45.800s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	45.950s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	48.220s	10.200us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.471s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.829s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.278s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.658s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.104m	16.335ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.175m	13.490ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	10.340s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.580s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.175m	13.490ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	13.604s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.605s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	13.443s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	13.383s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.130s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.104m	16.335ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.465m	8.524ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	8.091m	20.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.580m	12.015ms	0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.369m	30.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.362m	3.793ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.104m	16.335ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.415s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.368s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.104m	16.335ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs	12.798s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	10.989s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.369m	30.018ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.590s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.482s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.490s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.699s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.118s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.476s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.368s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	21.938s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.424s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	21.938s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	21.938s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	21.938s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.967m	10.133ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	27.143s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.036s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	16.783s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.824s		0	1	0.00
		chip_sw_lc_ctrl_transition	21.938s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.151m	20.010ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.993m	14.029ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	16.274s		0	1	0.00
		chip_prim_tl_access	10.638m	14.206ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.582s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.073s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.654s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.933s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.874s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.949s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.512s		0	1	0.00
		chip_rv_dm_lc_disabled	18.483m	29.295ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.553m	3.953ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	47.940s	10.220us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.978m	5.544ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.464m	3.251ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.759m	4.894ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	45.140s	10.100us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.069m	4.183ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.253m	3.592ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.880m	5.587ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	50.990s	10.300us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.151m	20.010ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	21.938s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	38.420s	10.140us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.120m	6.409ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.593m	5.050ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.208s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.208s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.164s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.020m	3.624ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	14.422s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.151m	20.010ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	54.550s	10.340us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.047s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.120s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.970m	5.636ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.970m	5.636ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.970m	5.636ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.237m	4.844ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.993m	14.029ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.993m	14.029ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	13.811s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.553s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.274s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.104m	16.335ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.312m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	21.938s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.237m	4.844ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.151m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	13.811s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	3.543m	3.304ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.237m	4.844ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.151m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	13.811s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	3.543m	3.304ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	21.938s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.787s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.424s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	27.143s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.036s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	16.783s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.824s		0	1	0.00
		chip_sw_lc_ctrl_transition	21.938s		0	1	0.00
		chip_prim_tl_access	10.638m	14.206ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	10.638m	14.206ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.426s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	14.291s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.829s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.120s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.940s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	45.140s	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	54.550s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	50.990s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.553s		0	1	0.00
		chip_sw_clkmgr_jitter	4.031m	4.919ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.348m	8.030ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.348m	8.030ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.231m	4.154ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.360m	3.644ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.467m	5.070ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.669m	5.836ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.226m	4.905ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.866m	4.638ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.543m	3.304ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	8.091m	20.016ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	8.091m	20.016ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.846m	4.739ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.765m	4.416ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.921m	3.962ms	1	1	100.00
		chip_sw_csrng_smoketest	3.433m	4.542ms	1	1	100.00
		chip_sw_gpio_smoketest	4.132m	6.019ms	1	1	100.00
		chip_sw_hmac_smoketest	4.544m	5.911ms	1	1	100.00
		chip_sw_kmac_smoketest	4.294m	6.093ms	1	1	100.00
		chip_sw_otbn_smoketest	4.958m	6.377ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	2.987m	5.716ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.727m	5.697ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.467m	4.808ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.389m	4.612ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.021m	4.084ms	1	1	100.00
		chip_sw_uart_smoketest	3.662m	5.059ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	17.443s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	18.143s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	12.983s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.248s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.256m	5.505ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.538m	6.024ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.883m	5.030ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.150m	4.927ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.352s		0	1	0.00
		chip_rv_dm_lc_disabled	18.483m	29.295ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	11.873s		0	1	0.00
		chip_sw_lc_walkthrough_prod	13.777s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	16.789s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.408s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.352s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	16.083s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.103s		0	1	0.00
		rom_volatile_raw_unlock	11.881s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.976s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.244m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.156m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.861m	4.160ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.861m	4.160ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	16.120s		0	1	0.00
		chip_same_csr_outstanding	10.300s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	16.120s		0	1	0.00
		chip_same_csr_outstanding	10.300s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	50.120s	43.327us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	10.560s	11.891us	1	1	100.00
		xbar_smoke_large_delays	4.746m	2.442ms	1	1	100.00
		xbar_smoke_slow_rsp	5.210m	1.947ms	1	1	100.00
		xbar_random_zero_delays	50.910s	44.578us	1	1	100.00
		xbar_random_large_delays	5.150m	2.578ms	1	1	100.00
		xbar_random_slow_rsp	20.207m	7.517ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	52.250s	115.594us	1	1	100.00
		xbar_error_and_unmapped_addr	29.310s	68.741us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	29.230s	32.493us	1	1	100.00
		xbar_error_and_unmapped_addr	29.310s	68.741us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	5.260m	758.181us	1	1	100.00
		xbar_access_same_device_slow_rsp	30.869m	11.849ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	17.560s	43.832us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.770m	98.089us	1	1	100.00
		xbar_stress_all_with_error	4.021m	777.550us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	9.821m	424.251us	1	1	100.00
		xbar_stress_all_with_reset_error	2.298m	160.259us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.283s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.703s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.739s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.339s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.182s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.995s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.232s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.698s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.357s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.223s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.054s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.750s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.419s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.891s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.596s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.055s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	13.858s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.304s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	14.244s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.188s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.953s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.428s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.994s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.948s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.423s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.586s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.585s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.946s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.412s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.695s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.772s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.671s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.332s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.502s		0	1	0.00
		rom_e2e_asm_init_dev	11.782s		0	1	0.00
		rom_e2e_asm_init_prod	11.099s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.251s		0	1	0.00
		rom_e2e_asm_init_rma	11.303s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.274s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.942s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.628s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.550s		0	1	0.00
V2		TOTAL			65	206	31.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.949m	5.198ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.245m	5.305ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.121s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.197s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.399s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.036s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.104m	16.335ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	13.828s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	13.646m	16.725ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	12.167s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.215s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.121s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.197s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.399s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.914s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.754s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.556s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.575m		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.941m	15.365ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.384m	3.554ms	1	1	100.00
		chip_sw_dma_abort	4.326m	5.362ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.860s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.732s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.068s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.938s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.787s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.855s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.267s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	13.049s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.698s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.476s		0	1	0.00
		chip_sw_mbx_smoketest	3.843m	4.357ms	1	1	100.00
		TOTAL			73	246	29.67

Failure Buckets

Job returned non-zero exit code has 145 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.177979049632568790791942530333004426535037036670628025655808632002812917070
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (266016)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (f145ac)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 76.624s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.61049676586862098665392503154455755971606217512491285346916747866478147344328
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (c9fab7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 147.806s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.34975764927399862125489182266922637855238852061034159037681642272306915930081
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (e62aaa)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 128.102s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.41563026980034421959073395605104089606041174714655229176555628294835243611874
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (7ab6a6)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 102.753s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.113316964291009601745925396448329653975010721975836140468987983659028220016440
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (5daf4c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 15.664s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 140 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.107779838713862330179998054796820907418363234318434056158640463058330124186559
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.40388209586548319808091287550869632894764657963397067222552274960286272423950
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.84501374100897775593975948227396135126174122479193528092998945408318912259022
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.33770819209493269946509807398053339301900439832818937295557431725141085728681
    Line 408, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.61621215631930091316965581866931174544129473517769492254860218664124793451253
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_sw_req has 1 failures.

0.chip_sw_rstmgr_sw_req.7324186411612624436890947531663986851917170193673853765467125252651109718553
Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest/run.log

  UVM_ERROR @ 12015.265892 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.265892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.19613448716712594162713696072826787598802501914771220592556346751297250748656
Line 443, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30018.366487 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30018.366487 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.86311705484872087348501652322704044920557725771820297786705856922982149099741
Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20016.085520 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20016.085520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.62204887672162704216951990422261776786390405702552100041588518576128205693929
Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18016.935539 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.935539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.100091272455887494891088467737929766317057346002221731751402480899802920445465
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.59695662137623801772461318075085194195122548124522044544853970419276124284517
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.54944600237297079084227674499420989451633330918076858361542520532379278757428
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.106082254941869720301407848644450004086000659292832401706888354493001148953360
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4600.863095 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hc2e47097  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h28  a_opcode: 'h0  a_user: 'h26966  d_param: 'h0  d_source: 'h28  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4600.863095 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.54301051911849049512414618809906584406994268501841321901634387096239962724290
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5366.939975 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hf5ec5d91  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h0  a_user: 'h2693a  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5366.939975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.3713920213100480032296916520680346925671641995681441950516748738811849705000
    Line 454, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3737.110392 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3737.110392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.89916065335382956984864156535180569955798594684495574351072832217428781741842
    Line 446, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  UVM_ERROR @ 16724.971904 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 16724.971904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.1813090872477706621039827314898479996482929282813341652923546516093725126546
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4153.934320 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4153.934320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.53439432530446697220957720866302186074288637513200185731506142254644249968932
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5835.893068 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5835.893068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage * key has 1 failures:
- Test chip_sw_keymgr_dpe_key_derivation has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation.64585567513953778758748457964363243411591941107904857056725583689426279637753
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
```
  UVM_FATAL @ 20010.280001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 1 failures:

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.11303449692190034715235084459904236713343658179798661567947083738623753360122
Line 459, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 10133.148584 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (17825629571352966376465542692713676253092320627498921415870693808600017923249 [0x2768f2e47599ee70a3df71dfb70deb81b16ff1353a7656c14e31126bf665ecb1] vs 13290409549545980012504569956332757184672798231518223991020640964059573913873 [0x1d621af0769b58cccc184121ce8bc31b0a55c07b4d82d2c5a6620034dce20911])
  UVM_INFO @ 10133.148584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.45649841573399433810695296583956918383270830342358496608764361646247545055919
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.21267334832264161257156767230457324272234784274089181985243269205784403540612
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4160.166834 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4160.166834 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.12743107111610634344293608242124523803414681024065232327434232158447613727657
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.95591306204876861500321878485276521254239742616851699313566642279130241475321
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5362.367556 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5362.367556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```