EDN Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.680s 35.302us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.630s 16.515us 1 1 100.00
V1 csr_rw edn_csr_rw 1.660s 35.581us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.450s 34.520us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.920s 42.361us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.050s 76.803us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.660s 35.581us 1 1 100.00
edn_csr_aliasing 1.920s 42.361us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.090s 68.746us 1 1 100.00
V2 csrng_commands edn_genbits 2.090s 68.746us 1 1 100.00
V2 genbits edn_genbits 2.090s 68.746us 1 1 100.00
V2 interrupts edn_intr 1.840s 75.555us 1 1 100.00
V2 alerts edn_alert 2.360s 80.098us 1 1 100.00
V2 errs edn_err 1.920s 19.508us 1 1 100.00
V2 disable edn_disable 1.630s 20.690us 1 1 100.00
edn_disable_auto_req_mode 1.950s 63.282us 1 1 100.00
V2 stress_all edn_stress_all 4.500s 2.091ms 1 1 100.00
V2 intr_test edn_intr_test 1.640s 18.185us 1 1 100.00
V2 alert_test edn_alert_test 1.650s 57.597us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.470s 208.821us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.470s 208.821us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.630s 16.515us 1 1 100.00
edn_csr_rw 1.660s 35.581us 1 1 100.00
edn_csr_aliasing 1.920s 42.361us 1 1 100.00
edn_same_csr_outstanding 2.020s 83.570us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.630s 16.515us 1 1 100.00
edn_csr_rw 1.660s 35.581us 1 1 100.00
edn_csr_aliasing 1.920s 42.361us 1 1 100.00
edn_same_csr_outstanding 2.020s 83.570us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.560s 5.552ms 1 1 100.00
edn_tl_intg_err 2.270s 176.516us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.810s 18.771us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.360s 80.098us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.560s 5.552ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.560s 5.552ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.560s 5.552ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.560s 5.552ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.360s 80.098us 1 1 100.00
edn_sec_cm 7.560s 5.552ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.360s 80.098us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.270s 176.516us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets