HMAC Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.760s 241.015us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.600s 24.252us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.690s 86.294us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.090s 1.225ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.060s 197.940us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.170s 57.122us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.690s 86.294us 1 1 100.00
hmac_csr_aliasing 5.060s 197.940us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 27.010s 626.927us 1 1 100.00
V2 back_pressure hmac_back_pressure 34.960s 904.191us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.929m 12.354ms 1 1 100.00
hmac_test_sha384_vectors 6.808m 12.294ms 1 1 100.00
hmac_test_sha512_vectors 19.730s 426.756us 1 1 100.00
hmac_test_hmac256_vectors 8.420s 431.856us 1 1 100.00
hmac_test_hmac384_vectors 9.010s 915.192us 1 1 100.00
hmac_test_hmac512_vectors 10.340s 2.053ms 1 1 100.00
V2 burst_wr hmac_burst_wr 1.650s 19.563us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.540s 260.341us 1 1 100.00
V2 error hmac_error 41.450s 923.368us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 30.110s 6.339ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.760s 241.015us 1 1 100.00
hmac_long_msg 27.010s 626.927us 1 1 100.00
hmac_back_pressure 34.960s 904.191us 1 1 100.00
hmac_datapath_stress 4.540s 260.341us 1 1 100.00
hmac_burst_wr 1.650s 19.563us 1 1 100.00
hmac_stress_all 56.490s 4.914ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.760s 241.015us 1 1 100.00
hmac_long_msg 27.010s 626.927us 1 1 100.00
hmac_back_pressure 34.960s 904.191us 1 1 100.00
hmac_datapath_stress 4.540s 260.341us 1 1 100.00
hmac_wipe_secret 30.110s 6.339ms 1 1 100.00
hmac_test_sha256_vectors 2.929m 12.354ms 1 1 100.00
hmac_test_sha384_vectors 6.808m 12.294ms 1 1 100.00
hmac_test_sha512_vectors 19.730s 426.756us 1 1 100.00
hmac_test_hmac256_vectors 8.420s 431.856us 1 1 100.00
hmac_test_hmac384_vectors 9.010s 915.192us 1 1 100.00
hmac_test_hmac512_vectors 10.340s 2.053ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.760s 241.015us 1 1 100.00
hmac_long_msg 27.010s 626.927us 1 1 100.00
hmac_back_pressure 34.960s 904.191us 1 1 100.00
hmac_datapath_stress 4.540s 260.341us 1 1 100.00
hmac_burst_wr 1.650s 19.563us 1 1 100.00
hmac_error 41.450s 923.368us 1 1 100.00
hmac_wipe_secret 30.110s 6.339ms 1 1 100.00
hmac_test_sha256_vectors 2.929m 12.354ms 1 1 100.00
hmac_test_sha384_vectors 6.808m 12.294ms 1 1 100.00
hmac_test_sha512_vectors 19.730s 426.756us 1 1 100.00
hmac_test_hmac256_vectors 8.420s 431.856us 1 1 100.00
hmac_test_hmac384_vectors 9.010s 915.192us 1 1 100.00
hmac_test_hmac512_vectors 10.340s 2.053ms 1 1 100.00
hmac_stress_all 56.490s 4.914ms 1 1 100.00
V2 stress_all hmac_stress_all 56.490s 4.914ms 1 1 100.00
V2 alert_test hmac_alert_test 1.730s 52.312us 1 1 100.00
V2 intr_test hmac_intr_test 1.460s 81.210us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.980s 48.585us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.980s 48.585us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.600s 24.252us 1 1 100.00
hmac_csr_rw 1.690s 86.294us 1 1 100.00
hmac_csr_aliasing 5.060s 197.940us 1 1 100.00
hmac_same_csr_outstanding 2.380s 338.966us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.600s 24.252us 1 1 100.00
hmac_csr_rw 1.690s 86.294us 1 1 100.00
hmac_csr_aliasing 5.060s 197.940us 1 1 100.00
hmac_same_csr_outstanding 2.380s 338.966us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.980s 96.138us 1 1 100.00
hmac_tl_intg_err 2.450s 442.814us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.450s 442.814us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.760s 241.015us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.130s 91.266us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.674m 7.367ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.270s 286.557us 1 1 100.00
TOTAL 28 28 100.00