I2C Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: `66485ba`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	18.570s	3.632ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.360s	1.431ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.520s	55.254us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.510s	28.300us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.990s	654.299us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.050s	54.045us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.690s	147.855us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.510s	28.300us	1	1	100.00
		i2c_csr_aliasing	2.050s	54.045us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.000s	170.155us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	8.520m	65.338ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	4.892m	27.785ms	1	1	100.00
V2	host_override	i2c_host_override	1.610s	96.992us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.760m	5.053ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	49.250s	4.880ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.610s	379.787us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.210s	1.658ms	1	1	100.00
		i2c_host_fifo_reset_rx	3.770s	489.738us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	48.470s	10.964ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.880s	3.396ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.370s	523.764us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.220s	7.553ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	2.342m	61.367ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.350s	2.894ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	14.040s	4.119ms	1	1	100.00
		i2c_target_intr_smoke	5.860s	1.200ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.740s	312.087us	1	1	100.00
		i2c_target_fifo_reset_tx	1.920s	200.937us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	3.800m	37.155ms	1	1	100.00
		i2c_target_stress_rd	14.040s	4.119ms	1	1	100.00
		i2c_target_intr_stress_wr	9.220s	8.000ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.060s	1.414ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	22.070s	1.737ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.730s	12.695ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.430s	385.219us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.670s	1.773ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.650s	153.278us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.892m	27.785ms	1	1	100.00
		i2c_host_perf_precise	2.170s	76.433us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.880s	3.396ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	15.140s	1.793ms	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.720s	6.677ms	1	1	100.00
		i2c_target_nack_acqfull_addr	3.200s	2.194ms	1	1	100.00
		i2c_target_nack_txstretch	1.980s	151.373us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.170s	211.747us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.490s	1.872ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.450s	17.660us	1	1	100.00
V2	intr_test	i2c_intr_test	1.480s	17.806us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.810s	582.543us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.810s	582.543us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.520s	55.254us	1	1	100.00
		i2c_csr_rw	1.510s	28.300us	1	1	100.00
		i2c_csr_aliasing	2.050s	54.045us	1	1	100.00
		i2c_same_csr_outstanding	1.720s	60.850us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.520s	55.254us	1	1	100.00
		i2c_csr_rw	1.510s	28.300us	1	1	100.00
		i2c_csr_aliasing	2.050s	54.045us	1	1	100.00
		i2c_same_csr_outstanding	1.720s	60.850us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.080s	127.573us	1	1	100.00
		i2c_sec_cm	1.700s	130.546us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.080s	127.573us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	34.300s	2.003ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.630s	330.759us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	20.230s	6.924ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.28623529337250880173259540884648390881495551888098519027474684597423945102789
    Line 90, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2002566063 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2002566063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.79592991388121751590463194369704641798162903914349954629863593054526911535480
    Line 104, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6924143774 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6924143774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.37676800029589637534930342393064315650860195685239669961544709013493199637307
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 330759334 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 330759334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.26869509253853348297526124829512764328156676087581952960883327023988962178095
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 523764024 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @35983

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
- Test i2c_target_nack_txstretch has 1 failures.
  - 0.i2c_target_nack_txstretch.74720812853435253889224445858577519031916990510092414302181529568657913604385
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 151372671 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 151372671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```