KEYMGR Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.920s	54.877us	1	1	100.00
V1	random	keymgr_random	3.420s	76.890us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.820s	114.437us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.720s	12.063us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.510s	3.407ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.730s	73.611us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.100s	566.258us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.720s	12.063us	1	1	100.00
		keymgr_csr_aliasing	3.730s	73.611us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	4.310s	94.712us	1	1	100.00
V2	sideload	keymgr_sideload	3.010s	344.714us	1	1	100.00
		keymgr_sideload_kmac	2.790s	326.276us	1	1	100.00
		keymgr_sideload_aes	2.970s	165.984us	1	1	100.00
		keymgr_sideload_otbn	2.920s	470.709us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	19.080s	3.036ms	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.700s	506.033us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.500s	75.167us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	39.380s	1.709ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.960s	369.012us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.280s	36.978us	1	1	100.00
V2	stress_all	keymgr_stress_all	47.650s	4.212ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.580s	129.999us	1	1	100.00
V2	alert_test	keymgr_alert_test	2.000s	14.681us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.760s	244.817us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.760s	244.817us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.820s	114.437us	1	1	100.00
		keymgr_csr_rw	1.720s	12.063us	1	1	100.00
		keymgr_csr_aliasing	3.730s	73.611us	1	1	100.00
		keymgr_same_csr_outstanding	2.170s	22.635us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.820s	114.437us	1	1	100.00
		keymgr_csr_rw	1.720s	12.063us	1	1	100.00
		keymgr_csr_aliasing	3.730s	73.611us	1	1	100.00
		keymgr_same_csr_outstanding	2.170s	22.635us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
		keymgr_tl_intg_err	3.400s	131.632us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.130s	604.375us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.130s	604.375us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.130s	604.375us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.130s	604.375us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	3.710s	1.093ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.400s	131.632us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.130s	604.375us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.310s	94.712us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.420s	76.890us	1	1	100.00
		keymgr_csr_rw	1.720s	12.063us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.420s	76.890us	1	1	100.00
		keymgr_csr_rw	1.720s	12.063us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.420s	76.890us	1	1	100.00
		keymgr_csr_rw	1.720s	12.063us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.700s	506.033us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.960s	369.012us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.960s	369.012us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.420s	76.890us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	5.440s	672.131us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.730s	114.034us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.700s	506.033us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.730s	114.034us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.730s	114.034us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.730s	114.034us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.930s	2.366ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.730s	114.034us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.480s	374.615us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.40601333096730350079659226540109834928146688321051439929429428141050834636014
      Line 891, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 374614548 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 374614548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---