| V1 |
smoke |
keymgr_dpe_smoke |
11.040s |
431.637us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.550s |
31.091us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.700s |
68.850us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
4.670s |
174.259us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
3.160s |
139.871us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
2.170s |
23.410us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.700s |
68.850us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.160s |
139.871us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.530s |
7.956us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.650s |
48.681us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
3.440s |
405.907us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
3.440s |
405.907us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.550s |
31.091us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.700s |
68.850us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.160s |
139.871us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.240s |
130.396us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.550s |
31.091us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.700s |
68.850us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.160s |
139.871us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.240s |
130.396us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
5.030s |
488.694us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
2.960s |
95.420us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
1.960s |
117.094us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
1.960s |
117.094us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
1.960s |
117.094us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
1.960s |
117.094us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
6.710s |
954.710us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
5.030s |
488.694us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
5.030s |
488.694us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |