KMAC/MASKED Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	34.730s	1.144ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.800s	21.992us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.780s	52.767us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.010s	1.801ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.720s	84.638us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.390s	191.081us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.780s	52.767us	1	1	100.00
		kmac_csr_aliasing	3.720s	84.638us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.630s	23.063us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.040s	22.221us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	8.935m	7.277ms	1	1	100.00
V2	burst_write	kmac_burst_write	20.868m	72.464ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.750s	11.325ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.580m	72.647ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.910s	932.199us	1	1	100.00
		kmac_test_vectors_sha3_512	17.987m	49.668ms	1	1	100.00
		kmac_test_vectors_shake_128	2.791m	40.220ms	1	1	100.00
		kmac_test_vectors_shake_256	1.637m	7.131ms	1	1	100.00
		kmac_test_vectors_kmac	2.820s	60.996us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.710s	110.602us	1	1	100.00
V2	sideload	kmac_sideload	24.860s	1.311ms	1	1	100.00
V2	app	kmac_app	1.294m	3.500ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.638m	71.682ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.276m	42.404ms	1	1	100.00
V2	error	kmac_error	3.191m	8.266ms	1	1	100.00
V2	key_error	kmac_key_error	6.500s	621.684us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	8.410s	223.430us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	23.360s	421.273us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	6.270s	1.494ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	17.720s	7.574ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.180s	65.383us	1	1	100.00
V2	stress_all	kmac_stress_all	20.243m	174.362ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.590s	20.971us	1	1	100.00
V2	alert_test	kmac_alert_test	1.680s	15.208us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.560s	74.663us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.560s	74.663us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.800s	21.992us	1	1	100.00
		kmac_csr_rw	1.780s	52.767us	1	1	100.00
		kmac_csr_aliasing	3.720s	84.638us	1	1	100.00
		kmac_same_csr_outstanding	2.180s	54.796us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.800s	21.992us	1	1	100.00
		kmac_csr_rw	1.780s	52.767us	1	1	100.00
		kmac_csr_aliasing	3.720s	84.638us	1	1	100.00
		kmac_same_csr_outstanding	2.180s	54.796us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.310s	192.128us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.310s	192.128us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.310s	192.128us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.310s	192.128us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.110s	43.522us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	39.730s	8.478ms	1	1	100.00
		kmac_tl_intg_err	3.890s	777.355us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.890s	777.355us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.180s	65.383us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	34.730s	1.144ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	24.860s	1.311ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.310s	192.128us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	39.730s	8.478ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	39.730s	8.478ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	39.730s	8.478ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	34.730s	1.144ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.180s	65.383us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	39.730s	8.478ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.259m	7.250ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	34.730s	1.144ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.111m	2.106ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.22828602880240512544766186060861120853732496533368994199723488029372934382328
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
        UVM_ERROR @  43522337 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_10_rd_A
        UVM_INFO @  43522337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---