ROM_CTRL/32KB Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.590s	178.415us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.880s	131.784us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.570s	311.375us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.420s	169.632us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.640s	134.200us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.360s	439.874us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.570s	311.375us	1	1	100.00
		rom_ctrl_csr_aliasing	4.640s	134.200us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	4.250s	126.460us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.310s	388.238us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.910s	312.044us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	16.310s	4.302ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	10.430s	1.042ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	4.170s	127.389us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.190s	387.738us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.190s	387.738us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.880s	131.784us	1	1	100.00
		rom_ctrl_csr_rw	4.570s	311.375us	1	1	100.00
		rom_ctrl_csr_aliasing	4.640s	134.200us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.950s	173.027us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.880s	131.784us	1	1	100.00
		rom_ctrl_csr_rw	4.570s	311.375us	1	1	100.00
		rom_ctrl_csr_aliasing	4.640s	134.200us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.950s	173.027us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	49.310s	2.656ms	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	17.560s	601.108us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.658m	617.874us	1	1	100.00
		rom_ctrl_tl_intg_err	22.170s	847.943us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.658m	617.874us	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.658m	617.874us	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	49.310s	2.656ms	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	49.310s	2.656ms	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	49.310s	2.656ms	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	49.310s	2.656ms	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	49.310s	2.656ms	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.658m	617.874us	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.658m	617.874us	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.590s	178.415us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.590s	178.415us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.590s	178.415us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	22.170s	847.943us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	49.310s	2.656ms	0	1	0.00
		rom_ctrl_kmac_err_chk	10.430s	1.042ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	49.310s	2.656ms	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	49.310s	2.656ms	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	49.310s	2.656ms	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	17.560s	601.108us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.658m	617.874us	1	1	100.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	23.980s	2.116ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.54325222339367438515959438551472154559872043195152065141246111960030980516069
      Line 102, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 2655784056 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 2655784056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---