ROM_CTRL/64KB Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.650s 546.139us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.550s 219.925us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.000s 221.952us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.220s 1.275ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.440s 699.141us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.180s 3.689ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.000s 221.952us 1 1 100.00
rom_ctrl_csr_aliasing 5.440s 699.141us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.650s 452.255us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.120s 303.329us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.350s 1.447ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 26.660s 7.164ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 18.140s 9.386ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.300s 300.808us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.320s 1.029ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.320s 1.029ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.550s 219.925us 1 1 100.00
rom_ctrl_csr_rw 6.000s 221.952us 1 1 100.00
rom_ctrl_csr_aliasing 5.440s 699.141us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.760s 308.326us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.550s 219.925us 1 1 100.00
rom_ctrl_csr_rw 6.000s 221.952us 1 1 100.00
rom_ctrl_csr_aliasing 5.440s 699.141us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.760s 308.326us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.155m 4.795ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.240s 2.120ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.567m 2.119ms 1 1 100.00
rom_ctrl_tl_intg_err 1.094m 573.553us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.567m 2.119ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.567m 2.119ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.155m 4.795ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.155m 4.795ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.155m 4.795ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.155m 4.795ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.155m 4.795ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.567m 2.119ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.567m 2.119ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.650s 546.139us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.650s 546.139us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.650s 546.139us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.094m 573.553us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.155m 4.795ms 1 1 100.00
rom_ctrl_kmac_err_chk 18.140s 9.386ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.155m 4.795ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.155m 4.795ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.155m 4.795ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.240s 2.120ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.567m 2.119ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 47.490s 1.660ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00