SPI_DEVICE/1R1W Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.338m	15.254ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.770s	52.589us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.440s	83.768us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.880s	4.833ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.790s	1.281ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.420s	258.387us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.440s	83.768us	1	1	100.00
		spi_device_csr_aliasing	6.790s	1.281ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.590s	12.305us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.220s	33.547us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.580s	23.026us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.590s	13.697us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.530s	8.412us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.730s	45.583us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.730s	45.583us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.940s	2.389ms	1	1	100.00
		spi_device_tpm_sts_read	1.570s	45.743us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	10.370s	3.553ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.570s	103.827us	1	1	100.00
		spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	15.190s	15.442ms	1	1	100.00
		spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	15.190s	15.442ms	1	1	100.00
		spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.620s	104.752us	1	1	100.00
		spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.620s	104.752us	1	1	100.00
		spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.620s	104.752us	1	1	100.00
		spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.620s	104.752us	1	1	100.00
		spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.620s	104.752us	1	1	100.00
		spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.510s	2.319ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.790s	371.172us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.790s	371.172us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.790s	371.172us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.650s	1.278ms	1	1	100.00
		spi_device_read_buffer_direct	8.090s	3.738ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.790s	371.172us	1	1	100.00
		spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	36.950s	3.103ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.590s	467.687us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.590s	467.687us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.338m	15.254ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.479m	17.675ms	1	1	100.00
V2	stress_all	spi_device_stress_all	42.490s	15.997ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.500s	15.106us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.560s	14.085us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.500s	560.748us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.500s	560.748us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.770s	52.589us	1	1	100.00
		spi_device_csr_rw	2.440s	83.768us	1	1	100.00
		spi_device_csr_aliasing	6.790s	1.281ms	1	1	100.00
		spi_device_same_csr_outstanding	3.630s	60.548us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.770s	52.589us	1	1	100.00
		spi_device_csr_rw	2.440s	83.768us	1	1	100.00
		spi_device_csr_aliasing	6.790s	1.281ms	1	1	100.00
		spi_device_same_csr_outstanding	3.630s	60.548us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.640s	46.178us	1	1	100.00
		spi_device_tl_intg_err	18.100s	2.091ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.100s	2.091ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	25.130s	3.939ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.107808236687556050294285559869370489365673792068528044071231164397579034254384
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  11125863 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[72])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  11125863 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  11125863 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[968])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.21932076747427467680890615441486676247501031553152174253041264458609777653523
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   7711346 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   7711346 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   7793346 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa3a7ac [101000111010011110101100] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   7793346 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xa3a7ac [101000111010011110101100] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])