SRAM_CTRL/MAIN Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	17.560s	3.579ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.560s	12.855us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.670s	12.871us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.890s	27.701us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.610s	33.859us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.330s	386.698us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.670s	12.871us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	33.859us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.847m	57.638ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.833m	23.129ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.704m	88.803ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.451m	3.995ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	38.388m	1.436s	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.321m	14.446ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	32.520s	19.641ms	1	1	100.00
V2	executable	sram_ctrl_executable	2.060m	20.841ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.400s	1.782ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.132m	3.559ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	21.200s	4.086ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	27.040s	959.397us	1	1	100.00
		sram_ctrl_throughput_w_readback	19.420s	1.626ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	33.970s	4.007ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.150s	1.540ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.065h	92.457ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.520s	90.810us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.520s	80.360us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.520s	80.360us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.560s	12.855us	1	1	100.00
		sram_ctrl_csr_rw	1.670s	12.871us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	33.859us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	36.790us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.560s	12.855us	1	1	100.00
		sram_ctrl_csr_rw	1.670s	12.871us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	33.859us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	36.790us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	17.470s	15.393ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.490s	6.989us	0	1	0.00
		sram_ctrl_tl_intg_err	2.760s	457.553us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.490s	6.989us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.760s	457.553us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.970s	4.007ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	33.970s	4.007ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.670s	12.871us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.060m	20.841ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.060m	20.841ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.060m	20.841ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	32.520s	19.641ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.900s	1.658ms	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	17.470s	15.393ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.680s	1.322ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	17.560s	3.579ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	17.560s	3.579ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.060m	20.841ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.490s	6.989us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	32.520s	19.641ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.490s	6.989us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.490s	6.989us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	17.560s	3.579ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.490s	6.989us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	37.500s	4.133ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.75266050457610233004002133295753473155232795222527367099306078161318277545172
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1658177824 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1658177824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.29845687641644115221303660130790441648838324618762358875747772578276090933823
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6988629 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6988629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---