SRAM_CTRL/RET Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 40.570s 2.785ms 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.690s 20.512us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.570s 28.634us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.830s 154.825us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.740s 18.871us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.510s 45.706us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.570s 28.634us 1 1 100.00
sram_ctrl_csr_aliasing 1.740s 18.871us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 8.710s 1.436ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.060s 193.438us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 44.230s 1.330ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 1.560m 1.338ms 1 1 100.00
V2 bijection sram_ctrl_bijection 52.030s 4.651ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 4.888m 5.840ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 5.630s 421.604us 1 1 100.00
V2 executable sram_ctrl_executable 2.925m 6.500ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 24.310s 1.601ms 1 1 100.00
sram_ctrl_partial_access_b2b 3.095m 38.658ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 4.550s 398.142us 1 1 100.00
sram_ctrl_throughput_w_partial_write 23.930s 416.033us 1 1 100.00
sram_ctrl_throughput_w_readback 2.530s 185.085us 1 1 100.00
V2 regwen sram_ctrl_regwen 6.531m 4.258ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 2.090s 71.113us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 28.982m 401.890ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.560s 13.908us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 3.290s 84.667us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 3.290s 84.667us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.690s 20.512us 1 1 100.00
sram_ctrl_csr_rw 1.570s 28.634us 1 1 100.00
sram_ctrl_csr_aliasing 1.740s 18.871us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.620s 44.529us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.690s 20.512us 1 1 100.00
sram_ctrl_csr_rw 1.570s 28.634us 1 1 100.00
sram_ctrl_csr_aliasing 1.740s 18.871us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.620s 44.529us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 2.590s 237.352us 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.970s 8.101us 0 1 0.00
sram_ctrl_tl_intg_err 2.530s 389.193us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.970s 8.101us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.530s 389.193us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 6.531m 4.258ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 6.531m 4.258ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.570s 28.634us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 2.925m 6.500ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 2.925m 6.500ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 2.925m 6.500ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 5.630s 421.604us 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 2.150s 200.522us 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 2.590s 237.352us 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 1.970s 27.969us 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 40.570s 2.785ms 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 40.570s 2.785ms 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 2.925m 6.500ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.970s 8.101us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 5.630s 421.604us 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.970s 8.101us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.970s 8.101us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 40.570s 2.785ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.970s 8.101us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 2.067m 14.769ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets