UART Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.520s	480.733us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.460s	38.489us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.490s	16.827us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.800s	536.750us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.700s	18.925us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.800s	23.012us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.490s	16.827us	1	1	100.00
		uart_csr_aliasing	1.700s	18.925us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.410m	159.649ms	1	1	100.00
V2	parity	uart_smoke	2.520s	480.733us	1	1	100.00
		uart_tx_rx	1.410m	159.649ms	1	1	100.00
V2	parity_error	uart_intr	26.970s	60.836ms	1	1	100.00
		uart_rx_parity_err	1.352m	69.723ms	1	1	100.00
V2	watermark	uart_tx_rx	1.410m	159.649ms	1	1	100.00
		uart_intr	26.970s	60.836ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.466m	71.816ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	16.400s	26.965ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	18.410s	14.391ms	1	1	100.00
V2	rx_frame_err	uart_intr	26.970s	60.836ms	1	1	100.00
V2	rx_break_err	uart_intr	26.970s	60.836ms	1	1	100.00
V2	rx_timeout	uart_intr	26.970s	60.836ms	1	1	100.00
V2	perf	uart_perf	8.230s	355.987us	1	1	100.00
V2	sys_loopback	uart_loopback	5.250s	10.161ms	1	1	100.00
V2	line_loopback	uart_loopback	5.250s	10.161ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	18.620s	54.880ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.300s	4.534ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.270s	1.343ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.410s	1.950ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.761m	83.904ms	1	1	100.00
V2	stress_all	uart_stress_all	5.525m	788.986ms	1	1	100.00
V2	alert_test	uart_alert_test	1.570s	43.986us	1	1	100.00
V2	intr_test	uart_intr_test	1.440s	44.099us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.060s	131.069us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.060s	131.069us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.460s	38.489us	1	1	100.00
		uart_csr_rw	1.490s	16.827us	1	1	100.00
		uart_csr_aliasing	1.700s	18.925us	1	1	100.00
		uart_same_csr_outstanding	1.650s	49.777us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.460s	38.489us	1	1	100.00
		uart_csr_rw	1.490s	16.827us	1	1	100.00
		uart_csr_aliasing	1.700s	18.925us	1	1	100.00
		uart_same_csr_outstanding	1.650s	49.777us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.590s	151.971us	1	1	100.00
		uart_tl_intg_err	2.110s	165.556us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.110s	165.556us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	33.850s	14.921ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00