CHIP Simulation Results

Thursday April 10 2025 17:01:13 UTC

GitHub Revision: `66485ba`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.256m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.256m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.231m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.108m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	44.076s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.587m	5.171ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.587m	5.171ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.587m	5.171ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.513m		0	1	0.00
		chip_sw_example_manufacturer	2.688m		0	1	0.00
		chip_sw_example_concurrency	4.099m	5.408ms	1	1	100.00
		chip_sw_uart_smoketest_signed	10.647s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.260s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	17.670s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	17.670s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.530s	12.203us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.751m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.273m	7.220ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.168m	5.176ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	14.444s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	14.314s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	35.089s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	15.147s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.840s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.840s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.332m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.102m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.669m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.669m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.884m	4.739ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.437m	5.196ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.223m	8.184ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.252s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.779s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	14.364m	16.993ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.740m	6.209ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.026m	18.014ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.026m	18.014ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	15.470s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	11.214s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	11.214s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	14.977s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.109m	5.321ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.384m	4.622ms	1	1	100.00
		chip_sw_aes_idle	4.340m	5.252ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.418m	5.413ms	1	1	100.00
		chip_sw_kmac_idle	3.467m	3.242ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	15.109s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.138s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.837s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.723s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.597s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.416s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.167s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.450s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.427s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.611s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.552s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.597s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.416s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.167s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.450s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.427s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.611s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.552s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.161s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.610s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.840s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	50.950s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.062m	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.777s		0	1	0.00
		chip_sw_clkmgr_jitter	3.468m	5.091ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.434m	3.824ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.182s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	53.950s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	52.020s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	45.930s	10.400us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	49.910s	10.120us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	50.710s	10.340us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.336s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.596s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	14.088s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	16.711s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.761m	15.346ms	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.065m	14.644ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	11.214s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.877s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.065m	14.644ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	12.692s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	13.730s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	13.777s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	20.461s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	14.122s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.761m	15.346ms	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.223m	8.184ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.477m	20.022ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.620m	12.027ms	0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.774m	30.017ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.846m	3.221ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.761m	15.346ms	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.755s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.259s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.761m	15.346ms	0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.913s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.774m	30.017ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	13.386s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.218s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.015s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.048s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.104s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.719s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.259s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	25.246s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	27.615s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	25.246s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	25.246s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	25.246s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.005m	20.010ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	37.486s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.750s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	37.091s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	28.189s		0	1	0.00
		chip_sw_lc_ctrl_transition	25.246s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.494m	20.010ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	10.979m	10.601ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.507s		0	1	0.00
		chip_prim_tl_access	5.302m	6.903ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.597s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.416s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.167s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.450s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.427s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.611s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.552s		0	1	0.00
		chip_rv_dm_lc_disabled	14.364m	16.993ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.733m	4.705ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	47.610s	10.200us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.541m	4.016ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.340m	5.252ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.347m	3.495ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	46.840s	10.200us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.418m	5.413ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.282m	3.956ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.488m	5.732ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.062m	10.380us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.494m	20.010ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	25.246s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	39.480s	10.320us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.600m	5.620ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.467m	3.242ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.444s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.444s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.481s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.196m	5.108ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	15.699s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.494m	20.010ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	50.950s	10.240us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	12.848s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.161s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.384m	4.622ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.384m	4.622ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.384m	4.622ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.716m	5.754ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.979m	10.601ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.979m	10.601ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.995m	7.674ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.777s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.507s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.761m	15.346ms	0	1	0.00
		chip_sw_data_integrity_escalation	2.669m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	25.246s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.716m	5.754ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.494m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.995m	7.674ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	4.357m	4.255ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.716m	5.754ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.494m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.995m	7.674ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	4.357m	4.255ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	25.246s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	14.946s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	27.615s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	37.486s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.750s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	37.091s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	28.189s		0	1	0.00
		chip_sw_lc_ctrl_transition	25.246s		0	1	0.00
		chip_prim_tl_access	5.302m	6.903ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.302m	6.903ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	32.113s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	25.483s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.596s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.161s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.610s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.840s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	50.950s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.062m	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.777s		0	1	0.00
		chip_sw_clkmgr_jitter	3.468m	5.091ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	6.847m	8.081ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	6.847m	8.081ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.584m	3.688ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.409m	4.307ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.944m	5.300ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.961m	6.870ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.910m	4.496ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.539m	6.008ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.357m	4.255ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.477m	20.022ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.477m	20.022ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.894m	5.645ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.491m	4.354ms	1	1	100.00
		chip_sw_clkmgr_smoketest	4.296m	5.632ms	1	1	100.00
		chip_sw_csrng_smoketest	4.289m	4.230ms	1	1	100.00
		chip_sw_gpio_smoketest	4.135m	3.949ms	1	1	100.00
		chip_sw_hmac_smoketest	5.335m	6.016ms	1	1	100.00
		chip_sw_kmac_smoketest	4.566m	4.948ms	1	1	100.00
		chip_sw_otbn_smoketest	5.573m	5.124ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	4.695m	5.341ms	1	1	100.00
		chip_sw_rv_plic_smoketest	4.058m	3.682ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.580m	4.992ms	1	1	100.00
		chip_sw_rstmgr_smoketest	4.158m	5.068ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.491m	3.636ms	1	1	100.00
		chip_sw_uart_smoketest	4.607m	5.618ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	18.772s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	10.647s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.751m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.139s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.146m	5.960ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.555m	4.699ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.786m	6.691ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.159m	4.824ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	13.625s		0	1	0.00
		chip_rv_dm_lc_disabled	14.364m	16.993ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.459s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.197s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	19.320s		0	1	0.00
		chip_sw_lc_walkthrough_rma	17.277s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	13.625s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	17.144s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.025s		0	1	0.00
		rom_volatile_raw_unlock	16.782s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	19.286s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.116m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	21.374s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.656m	3.845ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.656m	3.845ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	17.670s		0	1	0.00
		chip_same_csr_outstanding	9.540s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	17.670s		0	1	0.00
		chip_same_csr_outstanding	9.540s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.793m	300.097us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.730s	12.278us	1	1	100.00
		xbar_smoke_large_delays	3.861m	1.865ms	1	1	100.00
		xbar_smoke_slow_rsp	5.510m	2.113ms	1	1	100.00
		xbar_random_zero_delays	58.440s	52.439us	1	1	100.00
		xbar_random_large_delays	19.761m	11.650ms	1	1	100.00
		xbar_random_slow_rsp	9.804m	3.947ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	18.380s	13.110us	1	1	100.00
		xbar_error_and_unmapped_addr	42.760s	36.086us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.214m	200.664us	1	1	100.00
		xbar_error_and_unmapped_addr	42.760s	36.086us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.561m	391.820us	1	1	100.00
		xbar_access_same_device_slow_rsp	40.361m	17.076ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.978m	330.953us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.792m	183.202us	1	1	100.00
		xbar_stress_all_with_error	14.027m	2.787ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	7.687m	268.675us	1	1	100.00
		xbar_stress_all_with_reset_error	47.210s	36.777us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.997s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.384s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.028s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.123s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.741s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.386s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.487s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.251s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.456s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.842s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.426s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.666s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.254s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.334s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.464s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.568s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.302s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.782s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.271s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.103s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.314s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.309s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.931s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.640s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.111s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.220s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.616s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.111s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.106s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.711s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.467s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.934s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.880s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.218s		0	1	0.00
		rom_e2e_asm_init_dev	11.088s		0	1	0.00
		rom_e2e_asm_init_prod	11.494s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.812s		0	1	0.00
		rom_e2e_asm_init_rma	10.903s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.660s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.187s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.381s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.119s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.635m	5.335ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.800m	5.750ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.890s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.982s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.250s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.203s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.761m	15.346ms	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	15.671s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.710m	12.771ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.226s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.385s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.890s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.982s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.250s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.773s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.271s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.787s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.210m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.406m	14.108ms	1	1	100.00
		chip_plic_all_irqs_0	9.921m	5.667ms	1	1	100.00
		chip_plic_all_irqs_10	9.854m	6.698ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.329m	5.373ms	1	1	100.00
		chip_sw_dma_abort	4.149m	5.236ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.670s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.671s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.154s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.043s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.966s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.735s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.260s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.928s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.422s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.617s		0	1	0.00
		chip_sw_mbx_smoketest	5.625m	5.763ms	1	1	100.00
		TOTAL			75	247	30.36

Failure Buckets

Job returned non-zero exit code has 143 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.73488868290483579956744333407041625405750536007851307392105952681737575485965
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (c6fe22)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (e7d6da)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 71.794s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.19417403511133956156432415858638036863946759029461322704564298384827128495110
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (6498a3)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 143.258s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.88724954111393494091289334495734547844871357245945581667640244050037972570712
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (76448b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 149.818s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.106726919974803126043122406366136282910612031014973486990548972423961723551475
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (24f390)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.535s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.96107641420284252626451939720965949817610982199960907633180826215834415787406
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (c512d3)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 56.032s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 138 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.72521071659003914105900961658320467115001306061166141875298737434123912605264
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.14121383288809883332628444403842356422815121902642196442012704098519915982341
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.45541386007679077630244771726808024911638777992796327797694182125748775238786
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.114608945487628530827624980467710827637556004465518002834706302150071739684155
    Line 413, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.89458077817387738782478251691980521047344325011362513058541027572144306263077
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_sw_req has 1 failures.

0.chip_sw_rstmgr_sw_req.72013841582173733206678190386487666574103136342734163300454819095581424151885
Line 451, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest/run.log

  UVM_ERROR @ 12026.769375 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.769375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.48466639930096418298128925883476088211988984719276081324905694654232187593543
Line 447, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30017.106531 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30017.106531 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.100606405014186591094944386501806097592232556093632975693800902956952916151752
Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20021.563234 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20021.563234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.41698461194806118733685615862082117139135478790900302755149587642025542453804
Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18014.436303 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18014.436303 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.73210706235894033638310893272735909911701084370028739172040461562948085982376
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.9366880469840115186749702345470302177649433732093405040297388821426107102752
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.4883983205483130919635214691520514868696493556724772287090729771944722311935
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage * key has 2 failures:
- Test chip_sw_keymgr_dpe_key_derivation has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation.28889214088749027062579356356114855674182449385264306107476887938201864651535
    Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
```
  UVM_FATAL @ 20010.160001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_prod.22671068547231537275385388616027224827968784927983629751887547426577781991644
    Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 20010.240001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.102943229668044012571477349097181350700342150712886683610451320571754104589852
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4739.090782 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'haaf1ed3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h30  a_opcode: 'h1  a_user: 'h248ef  d_param: 'h0  d_source: 'h30  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4739.090782 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.72344331172362468682157500334233407407996582530043285175515379217006756024827
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5195.780244 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hb3c15443  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h0  a_user: 'h2696d  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5195.780244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.63348730868990990632740130770491563030657210030076504822645483274202367850669
    Line 584, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 15345.905298 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 15345.905298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.21469747002961481419517500479981431310202595542440273472516943985430502754654
    Line 468, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5175.827848 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5175.827848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.77124122079322477034097094492445441663656890945435307246356398693107359741648
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3688.275174 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3688.275174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.94842286663434780554775025763786063239090121326523164820588384286223801485599
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6870.426040 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6870.426040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.42474439970307352242102783679102823208020026345022010199895799572832745635477
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_sram_ctrl_scrambled_access has 1 failures.
  - 0.chip_sw_sram_ctrl_scrambled_access.100689431444954300111688552839977357836649992438836225256683307345974977606998
    Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest/run.log
```
  UVM_ERROR @ 7673.823672 us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 7673.823672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38222) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.80698224557047378904688169400715558298942449360288927937336391907080217540190
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3844.857064 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38222) { a_addr: 'h4044c  a_data: 'h247fcd25  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h1820f  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3844.857064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.47767301302689267026009930592525923840688030117194381108775629110698808482070
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.50799451588640829205763797253565992998749909873182030063431031904250736555711
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5235.558506 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5235.558506 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```