DMA Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	1.294ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	632.361us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	9.000s	303.729us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	28.522us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	16.882us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	831.045us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	319.765us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	31.376us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	16.882us	1	1	100.00
		dma_csr_aliasing	6.000s	319.765us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.817m	34.214ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	4.150m	20.790ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	28.250m	157.596ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	5.400m	26.366ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	4.150m	20.790ms	1	1	100.00
V2	dma_abort	dma_abort	12.000s	743.109us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.217m	6.736ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	131.561us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	33.604us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	33.604us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	28.522us	1	1	100.00
		dma_csr_rw	4.000s	16.882us	1	1	100.00
		dma_csr_aliasing	6.000s	319.765us	1	1	100.00
		dma_same_csr_outstanding	5.000s	80.850us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	28.522us	1	1	100.00
		dma_csr_rw	4.000s	16.882us	1	1	100.00
		dma_csr_aliasing	6.000s	319.765us	1	1	100.00
		dma_same_csr_outstanding	5.000s	80.850us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	23.000s	991.004us	1	1	100.00
		dma_generic_stress	5.400m	26.366ms	1	1	100.00
		dma_handshake_stress	4.150m	20.790ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	103.473us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.383m	39.409ms	1	1	100.00
		dma_longer_transfer	7.000s	501.997us	1	1	100.00
		TOTAL			21	21	100.00