EDN Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.930s 40.937us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.690s 70.832us 1 1 100.00
V1 csr_rw edn_csr_rw 1.650s 14.072us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.390s 1.175ms 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.810s 35.445us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.070s 431.953us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.650s 14.072us 1 1 100.00
edn_csr_aliasing 1.810s 35.445us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.350s 39.013us 1 1 100.00
V2 csrng_commands edn_genbits 2.350s 39.013us 1 1 100.00
V2 genbits edn_genbits 2.350s 39.013us 1 1 100.00
V2 interrupts edn_intr 1.820s 35.626us 1 1 100.00
V2 alerts edn_alert 1.810s 36.548us 1 1 100.00
V2 errs edn_err 1.810s 22.552us 1 1 100.00
V2 disable edn_disable 1.830s 16.675us 1 1 100.00
edn_disable_auto_req_mode 1.880s 19.435us 1 1 100.00
V2 stress_all edn_stress_all 1.920s 40.088us 1 1 100.00
V2 intr_test edn_intr_test 1.650s 53.519us 1 1 100.00
V2 alert_test edn_alert_test 1.670s 46.599us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.030s 440.795us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.030s 440.795us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.690s 70.832us 1 1 100.00
edn_csr_rw 1.650s 14.072us 1 1 100.00
edn_csr_aliasing 1.810s 35.445us 1 1 100.00
edn_same_csr_outstanding 1.720s 28.397us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.690s 70.832us 1 1 100.00
edn_csr_rw 1.650s 14.072us 1 1 100.00
edn_csr_aliasing 1.810s 35.445us 1 1 100.00
edn_same_csr_outstanding 1.720s 28.397us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.990s 2.302ms 1 1 100.00
edn_tl_intg_err 2.170s 544.049us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 2.010s 17.223us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.810s 36.548us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.990s 2.302ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.990s 2.302ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.990s 2.302ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.990s 2.302ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.810s 36.548us 1 1 100.00
edn_sec_cm 6.990s 2.302ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.810s 36.548us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.170s 544.049us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets