HMAC Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.110s 101.430us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.540s 60.527us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.610s 24.000us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.950s 2.094ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 7.030s 4.454ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.694m 118.458ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.610s 24.000us 1 1 100.00
hmac_csr_aliasing 7.030s 4.454ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 28.380s 726.067us 1 1 100.00
V2 back_pressure hmac_back_pressure 1.156m 1.874ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.420s 322.873us 1 1 100.00
hmac_test_sha384_vectors 5.447m 37.746ms 1 1 100.00
hmac_test_sha512_vectors 6.720m 16.299ms 1 1 100.00
hmac_test_hmac256_vectors 9.080s 275.351us 1 1 100.00
hmac_test_hmac384_vectors 8.560s 1.027ms 1 1 100.00
hmac_test_hmac512_vectors 8.810s 547.434us 1 1 100.00
V2 burst_wr hmac_burst_wr 7.690s 401.894us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 3.680m 1.738ms 1 1 100.00
V2 error hmac_error 23.250s 1.487ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 37.280s 5.627ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.110s 101.430us 1 1 100.00
hmac_long_msg 28.380s 726.067us 1 1 100.00
hmac_back_pressure 1.156m 1.874ms 1 1 100.00
hmac_datapath_stress 3.680m 1.738ms 1 1 100.00
hmac_burst_wr 7.690s 401.894us 1 1 100.00
hmac_stress_all 28.379m 88.007ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.110s 101.430us 1 1 100.00
hmac_long_msg 28.380s 726.067us 1 1 100.00
hmac_back_pressure 1.156m 1.874ms 1 1 100.00
hmac_datapath_stress 3.680m 1.738ms 1 1 100.00
hmac_wipe_secret 37.280s 5.627ms 1 1 100.00
hmac_test_sha256_vectors 8.420s 322.873us 1 1 100.00
hmac_test_sha384_vectors 5.447m 37.746ms 1 1 100.00
hmac_test_sha512_vectors 6.720m 16.299ms 1 1 100.00
hmac_test_hmac256_vectors 9.080s 275.351us 1 1 100.00
hmac_test_hmac384_vectors 8.560s 1.027ms 1 1 100.00
hmac_test_hmac512_vectors 8.810s 547.434us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.110s 101.430us 1 1 100.00
hmac_long_msg 28.380s 726.067us 1 1 100.00
hmac_back_pressure 1.156m 1.874ms 1 1 100.00
hmac_datapath_stress 3.680m 1.738ms 1 1 100.00
hmac_burst_wr 7.690s 401.894us 1 1 100.00
hmac_error 23.250s 1.487ms 1 1 100.00
hmac_wipe_secret 37.280s 5.627ms 1 1 100.00
hmac_test_sha256_vectors 8.420s 322.873us 1 1 100.00
hmac_test_sha384_vectors 5.447m 37.746ms 1 1 100.00
hmac_test_sha512_vectors 6.720m 16.299ms 1 1 100.00
hmac_test_hmac256_vectors 9.080s 275.351us 1 1 100.00
hmac_test_hmac384_vectors 8.560s 1.027ms 1 1 100.00
hmac_test_hmac512_vectors 8.810s 547.434us 1 1 100.00
hmac_stress_all 28.379m 88.007ms 1 1 100.00
V2 stress_all hmac_stress_all 28.379m 88.007ms 1 1 100.00
V2 alert_test hmac_alert_test 1.490s 23.263us 1 1 100.00
V2 intr_test hmac_intr_test 1.550s 12.283us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.070s 694.406us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.070s 694.406us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.540s 60.527us 1 1 100.00
hmac_csr_rw 1.610s 24.000us 1 1 100.00
hmac_csr_aliasing 7.030s 4.454ms 1 1 100.00
hmac_same_csr_outstanding 2.290s 143.346us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.540s 60.527us 1 1 100.00
hmac_csr_rw 1.610s 24.000us 1 1 100.00
hmac_csr_aliasing 7.030s 4.454ms 1 1 100.00
hmac_same_csr_outstanding 2.290s 143.346us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.000s 56.189us 1 1 100.00
hmac_tl_intg_err 2.180s 476.171us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.180s 476.171us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.110s 101.430us 1 1 100.00
V3 stress_reset hmac_stress_reset 5.610s 424.388us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.010m 8.655ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.880s 37.217us 1 1 100.00
TOTAL 28 28 100.00