I2C Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: `24bc68d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	14.010s	5.198ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.760s	1.388ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.680s	120.276us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.650s	54.147us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.320s	1.452ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.170s	140.554us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.770s	27.413us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.650s	54.147us	1	1	100.00
		i2c_csr_aliasing	2.170s	140.554us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.210s	204.237us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	35.613m	137.597ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	22.020s	2.670ms	1	1	100.00
V2	host_override	i2c_host_override	1.610s	15.945us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.028m	52.248ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	33.730s	3.371ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.730s	262.394us	1	1	100.00
		i2c_host_fifo_fmt_empty	13.870s	307.361us	1	1	100.00
		i2c_host_fifo_reset_rx	4.290s	203.647us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	32.350s	2.587ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	8.310s	690.820us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.420s	332.953us	1	1	100.00
V2	target_glitch	i2c_target_glitch	8.650s	9.618ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.741m	18.253ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.620s	2.321ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	33.270s	1.042ms	1	1	100.00
		i2c_target_intr_smoke	4.940s	861.446us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.510s	1.324ms	1	1	100.00
		i2c_target_fifo_reset_tx	1.630s	164.076us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	9.610s	13.888ms	1	1	100.00
		i2c_target_stress_rd	33.270s	1.042ms	1	1	100.00
		i2c_target_intr_stress_wr	45.660s	23.268ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.180s	3.183ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.730s	2.955ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.210s	5.025ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	4.310s	13.198ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.370s	258.202us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.710s	1.767ms	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	22.020s	2.670ms	1	1	100.00
		i2c_host_perf_precise	4.050s	327.285us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	8.310s	690.820us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	6.040s	528.974us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.540s	1.667ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.640s	1.948ms	1	1	100.00
		i2c_target_nack_txstretch	1.840s	503.300us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.650s	470.273us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.340s	425.464us	1	1	100.00
V2	alert_test	i2c_alert_test	1.430s	45.908us	1	1	100.00
V2	intr_test	i2c_intr_test	1.670s	34.265us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.080s	154.411us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.080s	154.411us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.680s	120.276us	1	1	100.00
		i2c_csr_rw	1.650s	54.147us	1	1	100.00
		i2c_csr_aliasing	2.170s	140.554us	1	1	100.00
		i2c_same_csr_outstanding	1.670s	35.404us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.680s	120.276us	1	1	100.00
		i2c_csr_rw	1.650s	54.147us	1	1	100.00
		i2c_csr_aliasing	2.170s	140.554us	1	1	100.00
		i2c_same_csr_outstanding	1.670s	35.404us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.790s	123.966us	1	1	100.00
		i2c_sec_cm	1.680s	75.783us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.790s	123.966us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.670s	3.757ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.010s	801.750us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	19.090s	746.530us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.38581542616892984488185584222461432124319647549481603331543957819952819088976
Line 161, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 137597046134 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @44587220

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.50617620687449346652797292564608584627543417265101345045219733664657668751907
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 801749860 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 230 [0xe6])
  UVM_INFO @ 801749860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.29822899401717430967850091547190888562184655968327370480456553168436317960793
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 13198017590 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 13198017590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.63881422033855625036347813960679429471195880684270873101136271533411885928213
    Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3756537645 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3756537645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:811) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.31293644103874124145863769326054083320627432895977732656764559789407479004018
    Line 104, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 746530318 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 746530318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```