KEYMGR Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.830s	195.177us	1	1	100.00
V1	random	keymgr_random	4.710s	98.890us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.220s	28.272us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.740s	59.177us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.050s	3.181ms	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	3.630s	279.922us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.410s	518.385us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.740s	59.177us	1	1	100.00
		keymgr_csr_aliasing	3.630s	279.922us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	4.350s	552.326us	1	1	100.00
V2	sideload	keymgr_sideload	2.900s	349.640us	1	1	100.00
		keymgr_sideload_kmac	3.070s	188.373us	1	1	100.00
		keymgr_sideload_aes	2.760s	36.057us	1	1	100.00
		keymgr_sideload_otbn	3.420s	220.261us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	7.160s	723.803us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.680s	44.457us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.210s	87.509us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.800s	123.223us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.320s	602.474us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.010s	132.265us	1	1	100.00
V2	stress_all	keymgr_stress_all	12.080s	1.504ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.870s	43.054us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.650s	18.410us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.690s	332.916us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.690s	332.916us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.220s	28.272us	1	1	100.00
		keymgr_csr_rw	1.740s	59.177us	1	1	100.00
		keymgr_csr_aliasing	3.630s	279.922us	1	1	100.00
		keymgr_same_csr_outstanding	2.180s	77.153us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.220s	28.272us	1	1	100.00
		keymgr_csr_rw	1.740s	59.177us	1	1	100.00
		keymgr_csr_aliasing	3.630s	279.922us	1	1	100.00
		keymgr_same_csr_outstanding	2.180s	77.153us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
		keymgr_tl_intg_err	3.560s	130.915us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.890s	816.134us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.890s	816.134us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.890s	816.134us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.890s	816.134us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.600s	187.659us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.560s	130.915us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.890s	816.134us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.350s	552.326us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.710s	98.890us	1	1	100.00
		keymgr_csr_rw	1.740s	59.177us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.710s	98.890us	1	1	100.00
		keymgr_csr_rw	1.740s	59.177us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.710s	98.890us	1	1	100.00
		keymgr_csr_rw	1.740s	59.177us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.680s	44.457us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.320s	602.474us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.320s	602.474us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.710s	98.890us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.720s	91.421us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.340s	227.486us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.680s	44.457us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.340s	227.486us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.340s	227.486us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.340s	227.486us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.340s	11.128ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.340s	227.486us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	4.510s	701.790us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			28	30	93.33

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.68976070733262754490141274546379882814117913610431202880488771164903348921149
      Line 421, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 701790225 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 701790225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.12242338395444639596920156984023182134240796477537588463789588947609528058085
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @ 3181263021 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @ 3181263021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---